Mario Porrmann

IEEE Access, 2024

FPGA Acceleration of DL-Based Real-Time DC Series Arc Fault Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

FPGA-based Acceleration of Deep Q-Networks with STANN-RL.

[BibT_eX]

[DOI]

Proceedings of the 2024 9th International Conference on Fog and Mobile Edge Computing (FMEC), 2024

2023

STANN - Synthesis Templates for Artificial Neural Network Inference and Training.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computational Intelligence, 2023

FeatSense - A Feature-Based Registration Algorithm with GPU-Accelerated TSDF-Mapping Backend for NVIDIA Jetson Boards.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International Conference on Robotic Computing, 2023

Towards 6D MCL for LiDARs in 3D TSDF Maps on Embedded Systems with GPUs.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International Conference on Robotic Computing, 2023

ReDroSe - Reconfigurable Drone Setup for Resource-Efficient SLAM.

[BibT_eX]

[DOI]

Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

Evaluation of heterogeneous AIoT Accelerators within VEDLIoT.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

VEDLIoT: Next generation accelerated AIoT systems and applications.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

ReconfROS: An approach for accelerating ROS nodes on reconfigurable SoCs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, October, 2022

A fully integrated system for hardware-accelerated TSDF SLAM with LiDAR sensors (HATSDF SLAM).

[BibT_eX]

[DOI]

Robotics Auton. Syst., 2022

VEDLIoT: Very Efficient Deep Learning in IoT.

[BibT_eX]

[DOI]

CoRR, 2022

A Survey of Domain-Specific Architectures for Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Access, 2022

VEDLIoT: Very Efficient Deep Learning in IoT.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

FAQ: A Flexible Accelerator for Q-Learning with Configurable Environment.

[BibT_eX]

[DOI]

Heinrich Theodor Vierhaus

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

ReconfROS: Running ROS on Reconfigurable SoCs.

[BibT_eX]

[DOI]

Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021

Energy-efficient FPGA-accelerated LiDAR-based SLAM for embedded robotics.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

HATSDF SLAM - Hardware-accelerated TSDF SLAM for Reconfigurable SoCs.

[BibT_eX]

[DOI]

Proceedings of the 10th European Conference on Mobile Robots, 2021

2019

FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2019

Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods.

[BibT_eX]

[DOI]

Sensors, 2019

2018

CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

OLT(RE)<sup>2</sup>: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems.

[BibT_eX]

[DOI]

CoRR, 2018

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on Indoor Positioning and Indoor Navigation, 2018

LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

M2DC - Modular Microserver DataCentre with heterogeneous hardware.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

FPGA-based multi-robot tracking.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

From CPU to FPGA - Acceleration of self-organizing maps for data mining.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Reconfigurable vision processing system for player tracking in indoor sports.

[BibT_eX]

[DOI]

Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016

Data centres for IoT applications: The M2DC approach (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Performance estimation of streaming applications for hierarchical MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

The M2DC Project: Modular Microserver DataCentre.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

System-Level Analysis of Network Interfaces for Hierarchical MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 65 nm standard cell library for ultra low-power applications.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Development of Self-optimizing Systems.

[BibT_eX]

[DOI]

Proceedings of the Design Methodology for Intelligent Technical Systems, 2014

The Paradigm of Self-optimization.

[BibT_eX]

[DOI]

Proceedings of the Design Methodology for Intelligent Technical Systems, 2014

Methods for the Design and Development.

[BibT_eX]

[DOI]

Proceedings of the Design Methodology for Intelligent Technical Systems, 2014

2013

A systematic approach for optimized bypass configurations for application-specific embedded processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing.

[BibT_eX]

[DOI]

Luca Sterpone

Hans Kristian Otnes Berge

IEEE Trans. Computers, 2013

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.

[BibT_eX]

[DOI]

Sven Lütkemeier

Thorsten Jungeblut

Snorre Aunet

IEEE J. Solid State Circuits, 2013

A reconfigurable neuroprocessor for self-organizing feature maps.

[BibT_eX]

[DOI]

Neurocomputing, 2013

Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

On-line testing of permanent radiation effects in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012

Optimizing inter-FPGA communication by automatic channel adaptation.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A 200mV 32b subthreshold processor with adaptive supply voltage control.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A TCMS-based architecture for GALS NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps.

[BibT_eX]

[DOI]

Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012

A scalable platform for run-time reconfigurable satellite payload processing.

[BibT_eX]

[DOI]

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

Design Optimizations for Tiled Partially Reconfigurable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms.

[BibT_eX]

[DOI]

Federico Nava

Donatella Sciuto

Stefan Herbrechtsmeier

Ulf Witkowski

ACM Trans. Reconfigurable Technol. Syst., 2011

Evaluation of Applied Intra-disk Redundancy Schemes to Improve Single Disk Reliability.

[BibT_eX]

[DOI]

Proceedings of the MASCOTS 2011, 2011

Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Analysis of SEU effects in partially reconfigurable SoPCs.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

Design Space Exploration for Memory Subsystems of VLIW Architectures.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

A Framework for the Design Space Exploration of Software-Defined Radio Applications.

[BibT_eX]

[DOI]

Proceedings of the Mobile Lightweight Wireless Systems, 2010

High level specification of embedded listeners for monitoring of Network-on-Chips.

[BibT_eX]

[DOI]

Paolo Roberto Grassi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Run-time reconfigurability in embedded multiprocessors.

[BibT_eX]

[DOI]

Madhura Purnaprajna

SIGARCH Comput. Archit. News, 2009

vMAGIC - Automatic Code Generation for VHDL.

[BibT_eX]

[DOI]

Christopher Pohl

Carlos Paiz

Int. J. Reconfigurable Comput., 2009

RAPTOR - A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

A Synchronization Method for Register Traces of Pipelined Processors.

[BibT_eX]

[DOI]

Proceedings of the Analysis, 2009

Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.

[BibT_eX]

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems.

[BibT_eX]

Paolo Roberto Grassi

Christopher Pohl

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Design optimizations to improve placeability of partial reconfiguration modules.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance.

[BibT_eX]

[DOI]

Madhura Purnaprajna

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008

Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography.

[BibT_eX]

[DOI]

Jamshid Shokrollahi

Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

SelfS - A real-time protocol for virtual ring topologies.

[BibT_eX]

[DOI]

André Brinkmann

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.

[BibT_eX]

[DOI]

Madhura Purnaprajna

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Resource efficiency of the GigaNetIC chip multiprocessor architecture.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

A design framework for FPGA-based dynamically reconfigurable digital controllers.

[BibT_eX]

[DOI]

Carlos Paiz

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.

[BibT_eX]

[DOI]

Vincenzo Rana

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs.

[BibT_eX]

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A Multiprocessor Cache for Massively Parallel SoC Architectures.

[BibT_eX]

[DOI]

Christian Liß

Proceedings of the Architecture of Computing Systems, 2007

2006

Application-Driven Development of Concurrent Packet Processing Platforms.

[BibT_eX]

[DOI]

Christian Sauer

Matthias Gries

Michael Thies

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Bio-inspired massively parallel architectures for nanotechnologies.

[BibT_eX]

[DOI]

Björn Jäger

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Dedicated module access in dynamically reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems.

[BibT_eX]

[DOI]

Proceedings of the Biologically Inspired Cooperative Computing, 2006

Reconfigurable hardware in-the-loop simulations for digital control design.

[BibT_eX]

Carlos Paiz

Christopher Pohl

Proceedings of the ICINCO 2006, 2006

A Layer Model for Systematically Designing Dynamically Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Relocation and Defragmentation for Heterogeneous Reconfigurable Systems.

[BibT_eX]

Markus Koester

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems, 2006

2005

A system approach for partially reconfigurable architectures.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2005

Defragmentation Algorithms for Partially Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

A Scalable Parallel SoC Architecture for Network Processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Placement-Oriented Modeling of Partially Reconfigurable Architectures.

[BibT_eX]

[DOI]

Markus Koester

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Component Case Study of a Self-Optimizing RCOS/RTOS System.

[BibT_eX]

[DOI]

Simon Oberthür

Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Adaptable Switch Boxes as On-Chip Routing Nodes for Networks-on-Chip.

[BibT_eX]

[DOI]

Ralf Eickhoff

Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Task Placement for Heterogeneous Reconfigurable Architectures.

[BibT_eX]

Markus Koester

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Context Saving and Restoring for Multitasking in Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Dynamic Reconfiguration of Real-Time Network Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Network Application Driven Instruction Set Extensions for Embedded Processing Clusters.

[BibT_eX]

[DOI]

Matthias Grünewald

Dinh Khoi Le

Uwe Kastens

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Hardware Accelerated Data Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

gNBX - reconfigurable hardware acceleration of self-organizing maps.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Study on column wise design compaction for reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

A Comparative Study on System Approaches for Partially Reconfigurable Architectures.

[BibT_eX]

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC.

[BibT_eX]

[DOI]

Matthias Grünewald

Proceedings of the 2004 Design, 2004

Leistungsbewertung unterschiedlicher Einbettungsvariaten dynamisch rekonfigurierbarer Hardware.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2004, 2004

2003

A massively parallel architecture for self-organizing feature maps.

[BibT_eX]

[DOI]

Ulf Witkowski

Friedhelm Meyer auf der Heide

IEEE Trans. Neural Networks, 2003

A holistic methodology for network processor design.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual IEEE Conference on Local Computer Networks (LCN 2003), 2003

2002

Leistungsbewertung eingebetteter Neurocomputersysteme.

[BibT_eX]

[DOI]

PhD thesis, 2002

Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

A reconfigurable SOM hardware accelerator.

[BibT_eX]

[DOI]

Proceedings of the 10th Eurorean Symposium on Artificial Neural Networks, 2002

2000

Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

1998

SOM accelerator system.

[BibT_eX]

[DOI]

Stefan Rüping

Neurocomputing, 1998

1997

A High Performance SOFM Hardware-System.

[BibT_eX]

[DOI]

Stefan Rüping