Mario Kovac

According to our database, Mario Kovac authored at least 27 papers between 1992 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

High-Performance Computing Storage Performance and Design Patterns - Btrfs and ZFS Performance for Different Use Cases.

Vedran Dakic, Mario Kovac, Igor Videc

Comput., June, 2024

2023

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.

Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal

ACM Trans. Archit. Code Optim., June, 2023

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit.

Mate Kovac, Leon Dragic, Branimir Malnar, Francesco Minervini, Oscar Palomar, Carlos Rojas, Mauro Olivieri, Josip Knezovic, Mario Kovac

Microprocess. Microsystems, March, 2023

2019

An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator.

Mate Cobrnic, Alen Duspara, Leon Dragic, Igor Piljic, Hrvoje Mlinaric, Mario Kovac

Proceedings of the Parallel Processing and Applied Mathematics, 2019

Bolt65 - performance-optimized HEVC HW/SW suite for Just-in-Time video processing.

Igor Piljic, Leon Dragic, Alen Duspara, Mate Cobrnic, Hrvoje Mlinaric, Mario Kovac

Proceedings of the 42nd International Convention on Information and Communication Technology, 2019

European processor initiative: the industrial cornerstone of EuroHPC for exascale era.

Mario Kovac

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni

Microprocess. Microsystems, 2018

Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation.

Arman Iranfar, Ali Pahlevan, Marina Zapater, Martin Zagar, Mario Kovac, David Atienza

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Thermal characterization of next-generation workloads on heterogeneous MPSoCs.

Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.

José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell

Proceedings of the Parallel Computing is Everywhere, 2017

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni

Proceedings of the Euromicro Conference on Digital System Design, 2017

2016

Enabling HPC for QoS-sensitive applications: The MANGO approach.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Work in progress: Embedded computer engineering learning platform capabilities.

Martin Zagar, Nikolina Frid, Josip Knezovic, Daniel Hofman, Mario Kovac, Vlado Sruk, Hrvoje Mlinaric

Proceedings of the IEEE Global Engineering Education Conference, 2015

The MANGO FET-HPC Project: An Overview.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni

Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014

E-Health Demystified: An E-Government Showcase.

Mario Kovac

Computer, 2014

Computer Engineering Laboratory Course: E2LP Platform Experience.

Nikolina Frid, Vlado Sruk, Hrvoje Mlinaric, Mario Kovac

Proceedings of the 2014 Embedded Engineering Learning Platform Workshop, 2014

Unified, multiple target, computer engineering learning platform.

Martin Zagar, Nikolina Frid, Josip Knezovic, Daniel Hofman, Mario Kovac, Vlado Sruk, Hrvoje Mlinaric

Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014

Power consumption and bandwidth savings with video transcoding to mobile device-specific spatial resolution.

Leon Dragic, Daniel Hofman, Mario Kovac, Martin Zagar, Josip Knezovic

Proceedings of the 9th International Symposium on Communication Systems, 2014

2006

Application of Dynamically Reconfigurable Processors in Digital Signal Processing.

Hrvoje Mlinaric, Mario Kovac, Josip Knezovic

Proceedings of the SIGMAP 2006, 2006

1998

Universal Strong Encryption FPGA Core Implementation.

Davor Runje, Mario Kovac

Proceedings of the 1998 Design, 1998

1995

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard.

Mario Kovac, N. Ranganathan

Proc. IEEE, 1995

JAGUAR: a high speed VLSI chip for JPEG image compression standard.

Mario Kovac, N. Ranganathan

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A prototype VLSI chip architecture for JPEG image compression.

Mario Kovac, N. Ranganathan, Martin Zagar

Proceedings of the 1995 European Design and Test Conference, 1995

1994

ACE: A VLSI Chip for Galois Field GF (2^m) Based Exponentiation.

Mario Kovac, N. Ranganathan

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm.

Mario Kovac, N. Ranganathan, M. Varanasi

IEEE Trans. Very Large Scale Integr. Syst., 1993

SIGMA: A VLSI Chip for Galois Field GF(2^m) Based Multiplication and Division.

Mario Kovac, N. Ranganathan, M. Varanasi

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

A Systolic Algorithm and Architecture for Galois Field Arithmetic.

Mario Kovac, N. Ranganathan, M. Varanasi

Proceedings of the 6th International Parallel Processing Symposium, 1992