Mario Garrido
Orcid: 0000-0001-5739-3544
According to our database1,
Mario Garrido
authored at least 53 papers
between 2006 and 2024.
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Bibliography
2024
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs.
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
J. Signal Process. Syst., April, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
Circuits Syst. Signal Process., 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems.
J. Signal Process. Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations.
J. Signal Process. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2014
Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications.
Proceedings of the 19th European Signal Processing Conference, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2007
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006