Mario Garrido

Orcid: 0000-0001-5739-3544

According to our database1, Mario Garrido authored at least 53 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Optimized 4-Parallel 1024-Point MSC FFT.
IEEE Access, 2024

Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs.
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024

2023
Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

CORDIC-Based Computation of Arcsine and Arccosine Functions on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices.
J. Signal Process. Syst., April, 2023

Radix-2<sup>k</sup> MSC FFT Architectures.
IEEE Access, 2023

Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
A Survey on Pipelined FFT Hardware Architectures.
J. Signal Process. Syst., 2022

Simplifying Karnaugh Maps by Making Groups of Non-power-of-two Elements.
Circuits Syst. Signal Process., 2022

2021
Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

The Constant Multiplier FFT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems.
J. Signal Process. Syst., 2020

Continuous-Flow Matrix Transposition Using Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Using Rotator Transformations to Simplify FFT Hardware Architectures.
IEEE Trans. Circuits Syst., 2020

A 128-Point Multi-Path SC FFT Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Evolution of the Performance of Pipelined FFT Architectures Through the Years.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Optimum Circuits for Bit-Dimension Permutations.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A 1 Million-Point FFT on a Single FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Effect of Finite Word-Length on SQNR, Area and Power for Real-Valued Serial FFT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations.
J. Signal Process. Syst., 2018

Optimal Single Constant Multiplication Using Ternary Adders.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Serial Commutator Fast Fourier Architecture for Real-Valued Signals.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Feedforward FFT Hardware Architectures Based on Rotator Allocation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Implementation approaches for 512-tap 60 GSa/s chromatic dispersion FIR filters.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Multiplierless Unity-Gain SDF FFTs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

CORDIC II: A New Improved CORDIC Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

The Serial Commutator FFT.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A New Representation of FFT Algorithms Using Triangular Matrices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

The Feedforward Short-Time Fourier Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2014
Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Challenging the limits of FFT performance on FPGAs (Invited paper).
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
Pipelined Radix-2<sup>k</sup> Feedforward FFT Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Low-complexity rotators for the FFT using base-3 signed stages.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Accurate Rotations Based on Coefficient Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Optimum Circuits for Bit Reversal.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications.
Proceedings of the 19th European Signal Processing Conference, 2011

A 512-point 8-parallel pipelined feedforward FFT for WPAN.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Alternatives for low-complexity complex rotators.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
A Pipelined FFT Architecture for Real-Valued Signals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2007
Efficient Memoryless Cordic for FFT Computation.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006


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