Mario Donato Marino

Orcid: 0000-0001-8336-9150

According to our database1, Mario Donato Marino authored at least 34 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
A Regularized Cross-Layer Ladder Network for Intrusion Detection in Industrial Internet of Things.
IEEE Trans. Ind. Informatics, 2023

A Sparse Sensor Placement Strategy Based on Information Entropy and Data Reconstruction for Ocean Monitoring.
IEEE Internet Things J., 2023

2022
An Evolutionary-Based Approach for Low-Complexity Intrusion Detection in Wireless Sensor Networks.
Wirel. Pers. Commun., 2022

A novel secure DV-Hop localization algorithm against wormhole attacks.
Telecommun. Syst., 2022

2020
Walter: Wide I/O Scaling of Number of Memory Controllers Versus Frequency and Voltage.
IEEE Access, 2020

2019
On parallelisation of image dehazing with OpenMP.
Int. J. Embed. Syst., 2019

2018
RAMON: Region-Aware Memory Controller.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Exploiting dynamic transaction queue size in scalable memory systems.
Soft Comput., 2018

An efficient algorithm for modelling and dynamic prediction of network traffic.
Int. J. Comput. Sci. Eng., 2018

2017
System implications of LLC MSHRs in scalable memory systems.
Microprocess. Microsystems, 2017

2016
Implications of shallower memory controller transaction queues in scalable memory systems.
J. Supercomput., 2016

Last level cache size heterogeneity in embedded systems.
J. Supercomput., 2016

ABaT-FS: Towards adjustable bandwidth and temperature via frequency scaling in scalable memory systems.
Microprocess. Microsystems, 2016

2014
Insights on memory controller scaling in multi-core embedded systems.
Int. J. Embed. Syst., 2014

2013
RFiof: an RF approach to I/O-pin and memory controller scalability for off-chip memories.
Proceedings of the Computing Frontiers Conference, 2013

2012
Adapted discrete-based entropy cache replacement algorithm.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

RFiop: RF-memory path to address on-package I/O pad and memory controller scalability.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

On-Package Scalability of RF and Inductive Memory Controllers.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2006
32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice.
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

L2-Cache Hierarchical Organizations for Multi-core Architectures.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

2004
Proposal of a Distributed Load Balancing Application for Managing Power in Grids.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

2003
A Preliminary Evaluation of the Speedup of a Distributed Simulator for Reliability Analysis.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

2002
DGWSDS: A Distributed Groundwater Simulator Dispersion System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

An Evaluation of the Speedup of a Preliminary Distributed MPI-Implementation for Groundwater Simulation Dispersion System.
Proceedings of the 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 2002

Evaluating the Speedup of a MPI-based Distributed Dispersion Simulator for Ground Water Systems.
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002

A Preliminary Proposal of a Complete Environment for Practical DSMs's Evaluation based on Benchmarks's Execution.
Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002

2000
Two Techniques for Improvement the Speedup of Nautilus DSM.
Computación y Sistemas, 2000

Techniques for Improving the Speedup of Nautilus DSM.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

An Evaluation of Page Aggregation Technique on Different DSM Systems.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Influence of the dynamic page aggregation on the speedup of Nautilus DSM system.
Proceedings of the Seventh International Conference on Parallel and Distributed Systems Workshops, 2000

A speedup comparative study: three third generation DSM systems.
Proceedings of the Seventh International Conference on Parallel and Distributed Systems Workshops, 2000

1999
A DSM Speedup Comparison: TreadMarks, JIAJIA and Nautilus.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

A Preliminary Speedup Comparison between Two Scope Consistency DSM Systems: JIAJIA and Nautilus.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999


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