Mario Auer
Orcid: 0000-0002-8120-275X
According to our database1,
Mario Auer
authored at least 18 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
An Integrated Analog Lock-In Amplifier using a Passive 3-Path Band-Pass Filter for a Fluxgate Sensor Readout Circuit.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
2022
Implementation of a Fully Differential Low Noise Current Source for Fluxgate Sensors.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 92-dB-DR 126-μν Sensitivity Potentiometrie Sensor Interface with High Interference Robustness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Self-Contained, Single-Chip Amperometric Measurement Platform for Biomedical Applications.
Proceedings of the 16th International Conference on Telecommunications, 2021
2020
Proceedings of the 43rd International Convention on Information, 2020
2019
Circuit Design and Verification Method of Integrated Sensor-Front-End Elements for Spaceborne Fluxgate Magnetometers.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Design Considerations for a Digital Input MEMS Speaker Audio Amplifier with Energy Recovery.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
A High Precision Digitally-Controlled Current Source for Magnetic-Field Measurements in Space.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Elektrotech. Informationstechnik, 2018
Elektrotech. Informationstechnik, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Elektrotech. Informationstechnik, 2016
2013
A process-variation compensation scheme to operate CMOS digital logic cells in deep sub-threshold region at 80mV.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
Switched capacitor DC-DC converter in 65nm CMOS technology with a peak efficiency of 97%.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2008
Elektrotech. Informationstechnik, 2008