Marina Deng
Orcid: 0000-0001-7964-1000
According to our database1,
Marina Deng
authored at least 12 papers
between 2018 and 2024.
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Bibliography
2024
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
2022
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2021
Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
0.4-μm InP/InGaAs DHBT with a 380-GHz ${f_{T}}$, > 600-GHz $f_{\max}$ and BVCE0 > 4.5 V.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Proceedings of the VLSI-SoC: Design Trends, 2020
2018
Proceedings of the 76th Device Research Conference, 2018