Marie-Minerve Louërat

Orcid: 0000-0001-9669-1085

Affiliations:
  • Sorbonne Université Paris, France
  • Université Pierre et Marie Curie, Paris, France


According to our database1, Marie-Minerve Louërat authored at least 64 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 10.8GS/s, 84MHz-BW RF Bandpass ΣΔ ADC with a 89dB-SFDR and a 62dB-SNDR for LTE/5G Receivers.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
Digital-to-Analog Hardware Trojan Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security.
IEEE Trans. Very Large Scale Integr. Syst., 2021

SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analog and Mixed-Signal IC Security via Sizing Camouflaging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

BIST-Assisted Analog Fault Diagnosis.
Proceedings of the 26th IEEE European Test Symposium, 2021

Breaking Analog Biasing Locking Techniques via Re-Synthesis.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A g<sub>m</sub>/I<sub>D</sub> Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A comprehensive in-depth study of tri-state inverter based DCO.
Microelectron. J., 2020

Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions.
Proceedings of the Forum for Specification and Design Languages, 2020

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism.
Proceedings of the IEEE European Test Symposium, 2020

Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Securing Programmable Analog ICs Against Piracy.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application.
Proceedings of the 16th International Conference on Synthesis, 2019

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

MixLock: Securing Mixed-Signal Circuits via Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An adaptive mesh refinement strategy of substrate modeling for smart power ICs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Mixed-signal PI controller in current-mode DC-DC buck converter for automotive applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Semi-automated analog placement.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Background analog and mixed signal calibration system for time-interleaved ADC.
Microelectron. J., 2015

Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations.
Integr., 2015

UVM-SystemC-AMS Framework for System-Level Verification and Validation of Automotive Use Cases.
IEEE Des. Test, 2015

Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

1.1-V 200 MS/s 12-bit digitally calibrated pipeline ADC in 40 nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Modeling, design and verification platform using SystemC AMS.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Split ADC digital background calibration for high speed SHA-less pipeline ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

UVM-SystemC-AMS based framework for the correct by construction design of MEMS in their real heterogeneous application context.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Hierarchical sizing and biasing of analog firm intellectual properties.
Integr., 2013

Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A structured DC analysis methodology for accurate verification of analog circuits.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Background time skew calibration for time-interleaved ADC using phase detection method.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

A unified platform for design and verification of mixed-signal systems based on SystemC AMS.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A Python-based layout-aware analog design methodology for nanometric technologies.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A seamless representation for coupling transistor sizing with nanometric CMOS layout generation.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Systematic design of continuous-time ΣΔ modulator with VCO-based quantizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Foreground digital calibration of non-linear errors in pipelined A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Automatic stress effects computation based on a layout generation tool for analog IC.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

Baseband fading channel simulator for Inter-Vehicle Communication using SystemC-AMS.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

SystemC-AMS Models for Low-Power Heterogeneous Designs: Application to a WSN for the Detection of Seismic Perturbations.
Proceedings of the ARCS '10, 2010

2009
Automatic Model Refinement of GmC Integrators for High-level Simulation of Continuous-time Sigma-Delta Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Q-enhanced LC bandpass filter using CAIRO+.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Simulation-based hierarchical sizing and biasing of analog firm IPs.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

2007
Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Optimizing Resistances and Capacitances of a Continuous-Time ΣΔ ADC.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
Loop delay compensation in bandpass continuous-time Sigma Delta modulators without additional feedback coefficients.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A language to desing generators of analog functions (poster).
Proceedings of the Forum on specification and Design Languages, 2004

Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators.
Proceedings of the 2004 Design, 2004

2002
Systematic approach for discrete-time to continuous-time transformation of Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Low-power design of low-voltage current-mode integrators for continuous-time Sigma-Delta modulators.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Switch sizing for very low-voltage switched-capacitor circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Systematic design of high-linearity current-mode integrators for low-power continuous-time ΣΔ modulators.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Analog design for reuse - case study: very low-voltage sigma-delta modulator.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Layout-Oriented Synthesis of High Performance Analog Circuits.
Proceedings of the 2000 Design, 2000


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