Marie Garcia Bardon

Orcid: 0000-0001-5772-5406

According to our database1, Marie Garcia Bardon authored at least 16 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2010
2012
2014
2016
2018
2020
2022
2024
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Links

On csauthors.net:

Bibliography

2024
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

DTCO for Fast STT-MRAM Periphery Operation.
Proceedings of the 20th International Conference on Synthesis, 2024

Automatic Regression Framework for MRAM Compact Models Calibration including Stochasticity.
Proceedings of the 20th International Conference on Synthesis, 2024

A DTCO Framework for 3D NAND Flash Readout.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021
Understanding the memory window in 1T-FeFET memories: a depolarization field perspective.
Proceedings of the IEEE International Memory Workshop, 2021

2016
5nm: Has the time for a device change come?
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015

Lateral NWFET optimization for beyond 7nm nodes.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Holisitic device exploration for 7nm node.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

2013
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.
Proceedings of the European Solid-State Device Research Conference, 2013

2010
Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2010


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