Marie Garcia Bardon
According to our database1,
Marie Garcia Bardon
authored at least 13 papers
between 2010 and 2024.
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Bibliography
2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
2022
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2021
Understanding the memory window in 1T-FeFET memories: a depolarization field perspective.
Proceedings of the IEEE International Memory Workshop, 2021
2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.
Proceedings of the European Solid-State Device Research Conference, 2013
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010