Murugesan Mariappan
Orcid: 0000-0002-3510-7110
According to our database1,
Murugesan Mariappan
authored at least 33 papers
between 2009 and 2024.
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Bibliography
2024
Characterization of Ozone-Ethylene Radical Pretreatment for Hybrid Bonding without Water Rinsing Processes.
Proceedings of the International 3D Systems Integration Conference, 2024
Impact of Cu Pad Density on Cu-CMP and Bonding Yield for Chip-to-Wafer Hybrid Bonding.
Proceedings of the International 3D Systems Integration Conference, 2024
Proceedings of the International 3D Systems Integration Conference, 2024
2023
Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
2021
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
2019
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2016
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.
Micromachines, 2016
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Development of via-last 3D integration technologies using a new temporary adhesive system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2011
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration.
Micromachines, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009