Mariagiovanna Sami
According to our database1,
Mariagiovanna Sami
authored at least 81 papers
between 1973 and 2016.
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Bibliography
2016
2014
IEEE Trans. Dependable Secur. Comput., 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocess. Microsystems, 2013
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013
2012
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Proceedings of the Information and Communication on Technology for the Fight against Global Warming, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2009
Creating an embedded systems program from scratch: nine years of experience at ALaRI.
Proceedings of the 2009 Workshop on Embedded Systems Education, 2009
2008
Modelling the power cost of security in Wireless Sensor Networks : The case of 802.15.4.
Proceedings of the 2008 International Conference on Telecommunications, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Self-adaptive Security at Application Level: a Proposal.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach.
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007
2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr., 2005
Des. Autom. Embed. Syst., 2005
Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations.
Proceedings of the 2005 International Conference on a World of Wireless, 2005
Proceedings of the 2005 Design, 2005
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor.
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005
2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
2003
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002
Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002
2001
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
1999
Proceedings of the 1999 Design, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Integr. Comput. Aided Eng., 1998
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
Proceedings of the 23rd EUROMICRO Conference '97, 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
1996
Proceedings of the conference on European design automation, 1996
Context Reorder Buffer: An Architectural Support for Real-Time Processing on RISC Architectures.
Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
J. Electron. Test., 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Synthesis of Multi-level Self-Checking Logic.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
System Level Policies for Fault Tolerance Issues in the FERMI Project.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
J. VLSI Signal Process., 1992
Microprocess. Microprogramming, 1992
1991
Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution.
Proc. IEEE, 1991
1990
Microprocessing and Microprogramming, 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
Fault-tolerance through reconfiguration of VLSI and WSI awards.
MIT Press series in computer systems, MIT Press, ISBN: 978-0-262-14044-7, 1989
1987
Microprocess. Microprogramming, 1987
1986
Computer, 1986
Proceedings of the Future Parallel Computers, 1986
1983
IEEE Trans. Software Eng., 1983
1982
Proceedings of the American Federation of Information Processing Societies: 1982 National Computer Conference, 1982
1973
Compression algorithms that preserve basic topological features in binary-coded patterns.
Pattern Recognit., 1973