Maria Theresa G. de Leon

According to our database1, Maria Theresa G. de Leon authored at least 35 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
A 288nV/√Hz low-noise capacitively-coupled instrumentation amplifier (CCIA) in 22-nm UTBB FD-SOI for signal conditioning of MEMS piezoresistive pressure sensors.
Proceedings of the 20th International SoC Design Conference, 2023

Comparison of hardware-optimized CNN and SVM models for human activity recognition using the HARTH and HAR 70 + datasets.
Proceedings of the 20th International SoC Design Conference, 2023

A high CMRR, high input impedance current-feedback instrumentation amplifier (CFIA) in 22-nm UTBB FD-SOI for signal conditioning of MEMS piezoresistive pressure sensors.
Proceedings of the 20th International SoC Design Conference, 2023

10 Gb/s Energy-efficient Optical Transceiver using 1060 nm HCG MEMS-tunable VCSEL in 28 nm FD-SOI Technology.
Proceedings of the 20th International SoC Design Conference, 2023

An EEG Analog Front-End Unit for Wearable Applications Implemented in 28nm FD-SOI.
Proceedings of the 20th International SoC Design Conference, 2023

2021
A CMOS Power Management Unit with Undervoltage Lockout Circuit as Startup for Piezoelectric Energy Harvesting Applications.
Proceedings of the 18th International SoC Design Conference, 2021

Asymmetric Charge Transfer Scheme Model in ML-SSHC with Consistent Power Extraction Improvement for Piezoelectric Energy Harvesters.
Proceedings of the 18th International SoC Design Conference, 2021

2020
Power and Area Oriented Implementations of Lightweight Cryptographic Algorithms for Wireless Sensor Networks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020


Designing a Class E Power Amplifier through Modeling in Verilog-A.
Proceedings of the International SoC Design Conference, 2020

5 Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65 nm CMOS.
Proceedings of the International SoC Design Conference, 2020

An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction.
Proceedings of the International SoC Design Conference, 2020

Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache.
Proceedings of the International SoC Design Conference, 2020

A Top-Down Approach for Low Noise Amplifier Design using Verilog-A.
Proceedings of the International SoC Design Conference, 2020

An Energy-Efficient Temperature Sensor Using CMOS Thyristor Delay Elements.
Proceedings of the 32nd International Conference on Microelectronics, 2020

High Contrast Gratings (HCG) MEMS-Tunable VCSEL Compact Model.
Proceedings of the 32nd International Conference on Microelectronics, 2020

2019
A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process.
J. Low Power Electron., 2019

Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes.
Proceedings of the 2019 International SoC Design Conference, 2019

An SDR-based WSN Testbed for RF Front End Simulation and Experimentation.
Proceedings of the 2019 International SoC Design Conference, 2019

Implementation of 6LoWPAN and Controller Area Network for a Smart Hydroponics System.
Proceedings of the 2019 Global IoT Summit, 2019

2018
A Study on the Effectiveness of Using a Hybrid Topology in Improving the Power Efficiency and Voltage Regulation over a Wide Input Range of DC-DC Converters.
Proceedings of the TENCON 2018, 2018

A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology.
Proceedings of the TENCON 2018, 2018

Hardware-Based Model of Node Clustering Using Q-Learning for Wireless Sensor Networks.
Proceedings of the TENCON 2018, 2018

A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications.
Proceedings of the TENCON 2018, 2018

An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process.
Proceedings of the TENCON 2018, 2018

A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks.
Proceedings of the TENCON 2018, 2018

Design of Multiple Prediction Complexity Configurations for an FPGA-Based H.264 Baseline Profile Encoder.
Proceedings of the TENCON 2018, 2018

Low Power Converter for Capacitive Sensors Using Capacitance-to-Pulse Width Modulation.
Proceedings of the TENCON 2018, 2018

Design and Implementation of a Thermoelectric Energy Harvesting Interface Circuit with Maximum Power Point Tracking and Self-Startup Capability for Wireless Sensor Nodes.
Proceedings of the TENCON 2018, 2018

A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications.
Proceedings of the TENCON 2018, 2018


2014
Efficiency improvement in MEMS thermoelectric generators employing solar concentration.
PhD thesis, 2014

2010
Comparison of LNA Topologies for WiMAX Applications in a Standard 90-nm CMOS Process.
Proceedings of the 12th UKSim, 2010

A 3rd Order Butterworth Gm-C Filter for WiMAX Receivers in a 90nm CMOS Process.
Proceedings of the 12th UKSim, 2010


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