Maria D. Vieira

Orcid: 0000-0003-3121-5103

According to our database1, Maria D. Vieira authored at least 3 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots.
IEEE Des. Test, 2022

2021
RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019
READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications.
ACM Trans. Embed. Comput. Syst., 2019


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