Maria D. Vieira

According to our database, Maria D. Vieira authored at least 4 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Robustness Analysis of Atomic Silicon Quantum Dot Logic Gates.

Arthur M. Fortini, João Gabriel O. Bicalho, Omar P. Vilela Neto, Maria D. Vieira, José Augusto Miranda Nacif, Ricardo S. Ferreira

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2022

Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots.

Maria D. Vieira, Samuel S. H. Ng, Marcel Walter, Robert Wille, Konrad Walus, Ricardo S. Ferreira, Omar P. Vilela Neto, José Augusto Miranda Nacif

IEEE Des. Test, 2022

2021

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays.

Maria D. Vieira, Michael Canesche, Lucas Bragança, Josué Campos, Mateus Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019

READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications.

Lucas Bragança da Silva, Ricardo S. Ferreira, Michael Canesche, Marcelo M. Menezes, Maria D. Vieira, Jeronimo Costa Penha, Peter Jamieson, José Augusto Miranda Nacif

ACM Trans. Embed. Comput. Syst., 2019