Marcos Martínez Peiró

According to our database, Marcos Martínez Peiró authored at least 9 papers between 2003 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management.

Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve

Microprocess. Microsystems, 2008

2006

An active methodology for teaching electronic systems design.

Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero

IEEE Trans. Educ., 2006

2004

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices.

Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró

Microprocess. Microsystems, 2004

2D-DCT on FPGA by polynomial transformation in two-dimensions.

Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Architectures for ICT on FPGA.

Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

FPGA Custom DSP for ECG Signal Analysis and Compression.

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer

Proceedings of the Field Programmable Logic and Application, 2004

2003

2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions.

Arturo Méndez Patiño, Marcos Martínez Peiró

Proceedings of the IFIP VLSI-SoC 2003, 2003

A new inverse discrete wavelet packet transform architecture.

Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA.

Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003