Marco Zanuso

According to our database¹, Marco Zanuso authored at least 14 papers between 2007 and 2011.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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On csauthors.net:

Bibliography

2011

Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs<sub>rms</sub> Integrated Jitter at 4.5-mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2010

A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Time-to-digital converter with 3-ps resolution and digital linearization algorithm.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Noise Analysis and Minimization in Bang-Bang Digital PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A glitch-corrector circuit for low-spur ADPLLs.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An all-digital architecture for low-jitter regulated delay lines.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007

Quantization Effects in All-Digital Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Marco Zanuso

Timeline

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