Marco Solieri

Orcid: 0000-0003-4531-2633

Affiliations:
  • Paris 13 University, Computer Science Laboratory of Paris-North University (LIPN)
  • University of Bologna, Computer Science and Engineering Department (DISI)


According to our database1, Marco Solieri authored at least 19 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2024
HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper).
Proceedings of the Fifth Workshop on Next Generation Real-Time Embedded Systems, 2024

2023
Time-sensitive autonomous architectures.
Real Time Syst., December, 2023

Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs.
ACM Trans. Embed. Comput. Syst., 2023

2022
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies.
IEEE Des. Test, 2022

2021
The Predictable Execution Model in Practice: Compiling Real Applications for COTS Hardware.
ACM Trans. Embed. Comput. Syst., 2021

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms.
IEEE Access, 2021

2020
Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms.
Proceedings of the 26th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2020

Evaluating Controlled Memory Request Injection to Counter PREM Memory Underutilization.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2020

Bao: A Lightweight Static Partitioning Hypervisor for Modern Multi-Core Embedded Systems.
Proceedings of the Workshop on Next Generation Real-Time Embedded Systems, 2020

A Systematic Assessment of Embedded Neural Networks for Object Detection.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

Real-Time Virtualization For Industrial Automation.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

2019
API Comparison of CPU-To-GPU Command Offloading Latency on Embedded Platforms (Artifact).
Dagstuhl Artifacts Ser., 2019

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems.
Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium, 2019

Novel Methodologies for Predictable CPU-To-GPU Command Offloading.
Proceedings of the 31st Euromicro Conference on Real-Time Systems, 2019

2018
Geometry of resource interaction and Taylor-Ehrhard-Regnier expansion: a minimalist approach.
Math. Struct. Comput. Sci., 2018

The Key Role of Memory in Next-Generation Embedded Systems for Military Applications.
Proceedings of 6th International Conference in Software Engineering for Defence Applications, 2018

2017
Is the Optimal Implementation Inefficient? Elementarily Not.
Proceedings of the 2nd International Conference on Formal Structures for Computation and Deduction, 2017

2016
Sharing, Superposition and Expansion: Geometrical Studies on the Semantics and Implementation of λ-calculi and Proof-nets. (Partage, superposition et développement : Études géométriques sur la sémantique et l'implémentation de lambda calculs et de réseaux de preuves / Condivisione, sovrapposizione e sviluppo: Studi geometrici sulla semantica e l'implementazione di lambda-calcoli e reti di dimostrazioni).
PhD thesis, 2016

2014
Geometry of Resource Interaction - A Minimalist Approach.
Proceedings of the Proceedings Third International Workshop on Linearity, 2014


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