Marco Restifo
Orcid: 0000-0003-1729-7237
According to our database1,
Marco Restifo
authored at least 15 papers
between 2017 and 2020.
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Bibliography
2020
Applicative System Level Test introduction to Increase Confidence on Screening Quality.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2018
J. Low Power Electron., 2018
J. Electron. Test., 2018
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017