Marco Ottavi

IEEE Trans. Emerg. Top. Comput., 2021

Soft Error Tolerant Count Min Sketches.

[BibT_eX]

[DOI]

Pedro Reviriego

Jorge Martínez

Sebastian Ignacio Peradotto Ibarra

IEEE Trans. Computers, 2021

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Reliability Assessment of Memristor based Gas Sensor Array.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Yield Estimation of a Memristive Sensor Array.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Microprocessor Protection Architecture against Hardware Trojans in Memories.

[BibT_eX]

[DOI]

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Memristor Based Planar Tunable RF Circuits.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

Design and Implementation of a Flexible Interface for TID Detector.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Fault Modeling and Simulation of Memristor based Gas Sensors.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Perovskite based Low Power Synaptic Memristor Device for Neuromorphic application.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Characterization of a RISC-V Microcontroller Through Fault Injection.

[BibT_eX]

[DOI]

Dario Asciolla

Luigi Dilillo

Douglas A. dos Santos

Douglas R. Melo

Alessandra Menicucci

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era.

[BibT_eX]

[DOI]

Giorgio Di Natale

IEEE Trans. Emerg. Top. Comput., 2018

Opcode vector: An efficient scheme to detect soft errors in instructions.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Memristor based adaptive impedance and frequency tuning network.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility.

[BibT_eX]

[DOI]

Alessandro Scaramella

Simone Stramaccioni

Alessia Zibecchi

Carla Andreani

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Two dimensional FFT architecture based on radix-4<sup>3</sup> algorithm with efficient output reordering.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Complementary Resistive Switch Sensing.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

The Case for RISC-V in Space.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures.

[BibT_eX]

[DOI]

Ronald F. DeMara

Marco Platzner

IEEE Trans. Emerg. Top. Comput., 2017

Reliable gas sensing with memristive array.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

High-energy neutrons characterization of a safety critical computing system.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Detecting errors in instructions with bloom filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

Qualitative techniques for System-on-Chip test with low-energy protons.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams.

[BibT_eX]

[DOI]

Filippo Giuliani

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A novel method for SEE validation of complex SoCs using Low-Energy Proton beams.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015

A Synergetic Use of Bloom Filters for Error Detection and Correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Dependable Multicore Architectures at Nanoscale: The View From Europe.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

IEEE Des. Test, 2015

2T2M memristor based TCAM cell for low power applications.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

A method to protect Bloom filters from soft errors.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation.

[BibT_eX]

[DOI]

Senwen Kan

Jennifer Dworak

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics.

[BibT_eX]

[DOI]

Daniele Felici

Sandro Bonacini

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Efficient implementation of error correction codes in hash tables.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Using memristor state change behavior to identify faults in photovoltaic arrays.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Characterization of data retention faults in DRAM devices.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Complementary resistive switch based stateful logic operations using material implication.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Error Detection and Correction in Content Addressable Memories by Using Bloom Filters.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Error detection in ternary CAMs using bloom filters.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A novel write-scheme for data integrity in memristor-based crossbar memories.

[BibT_eX]

[DOI]

Angelo Giuseppe Ruotolo

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

On the design of two single event tolerant slave latches for scan delay testing.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Feedback based droop mitigation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

High throughput and low power dissipation in QCA pipelines using Bennett clocking.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Error Detection and Correction in Content Addressable Memories.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Modeling Open Defects in Nanometric Scale CMOS.

[BibT_eX]

[DOI]

Anant Narayan Hariharan

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2009

2008

Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Serial Memory by Quantum-Dot Cellular Automata (QCA).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Analysis and Evaluations of Reliability of Reconfigurable FPGAs.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

2007

QCA Circuits for Robust Coplanar Crossing.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Evaluating the Yield of Repairable SRAMs for ATE.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2006

Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

HDLQ: A HDL environment for QCA design.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2006

Localization of Faults in Radix-n Signed Digit Adders.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Reliability Evaluation of Repairable/Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Novel designs for thermally robust coplanar crossing in QCA.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Tile-based QCA design using majority-like logic primitives.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2005

A Comparative Evaluation of Designs for Reliable Memory Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Design of a QCA Memory with Parallel Read/Serial Write.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Tile-based design of a serial memory in QCA.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Modeling QCA Defects at Molecular-level in Combinational Circuits.

[BibT_eX]

[DOI]

Mariam Momenzadeh

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Markov Models of Fault-Tolerant Memory Systems under SEU.

[BibT_eX]

[DOI]

Luca Schiano

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Simulation of reconfigurable memory core yield.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

On The Yield of Compiler-Based eSRAMs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.

[BibT_eX]

[DOI]

Xiaopeng Wang

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Data Integrity Evaluations of Reed Solomon Codes for Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Design of a fault tolerant solid state mass memory.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

A fault tolerant hardware based file system manager for solid state mass memory.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Yield Analysis of Compiler-Based Arrays of Embedded SRAMs.

[BibT_eX]

[DOI]

Xiaopeng Wang

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

A self-checking cell logic block for fault tolerant FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Bit Flip Injection in Processor-Based Architectures: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

Development of a dynamic routing system for a fault tolerant solid state mass memory.

[BibT_eX]

[DOI]

Panfilo Marinucci

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture.

[BibT_eX]

[DOI]

P. Marinucci