Marco Mestice
Orcid: 0000-0003-2975-3471
According to our database1,
Marco Mestice
authored at least 9 papers
between 2019 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology.
IEEE Trans. Instrum. Meas., 2024
2023
A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications.
IEEE Access, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2022
A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS Technology.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
2020
Sensors, 2020
2019
Analysis and Simulation of a PLL Architecture Towards a Fully Integrated 65 nm Solution for the New Spacefibre Standard.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019