Marco Garampazzi

According to our database, Marco Garampazzi authored at least 9 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.

Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process.

Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, T. Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET.

R. L. Nguyen, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, F. Ahmad, Fredy Solis, Gabriele Minoia, Geoff Hatcher, M. Bachu, Marco Garampazzi, Mohsen Hassanpourghadi, N. Fan, P. Prabha, S. Fan, S. Ho, T. Dusatko, Tzu-Fan Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm.

F. Ahmad, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, Fredy Solis, Gabriele Minoia, Geoff Hatcher, Hugo S. Carrer, K. Kota, L. Wang, M. Bachu, Marco Garampazzi, M. Hassanpourghadi, N. Fan, P. Prabha, R. L. Nguyen, S. Ho, T. Dusatko, T. Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2020

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.

Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani

IEEE J. Solid State Circuits, 2020

2019

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.

Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering.

Marco Garampazzi, Paulo M. Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello

IEEE J. Solid State Circuits, 2015

2014

An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators.

Marco Garampazzi, Stefano Dal Toso, Antonio Liscidini, Danilo Manstretta, P. Mendez, Luca Romanò, Rinaldo Castello

IEEE J. Solid State Circuits, 2014

A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering.

Marco Garampazzi, Paulo M. Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello

Proceedings of the ESSCIRC 2014, 2014