Marco Garampazzi
According to our database1,
Marco Garampazzi
authored at least 9 papers
between 2014 and 2024.
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Bibliography
2024
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2020
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2020
2019
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2015
Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering.
IEEE J. Solid State Circuits, 2015
2014
An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators.
IEEE J. Solid State Circuits, 2014
Proceedings of the ESSCIRC 2014, 2014