Marco Donato
Orcid: 0000-0002-9354-3447
According to our database1,
Marco Donato
authored at least 24 papers
between 2012 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Heterogeneous Memory Integration and Optimization for Energy-Efficient Multi-Task NLP Edge Inference.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
2023
A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs.
IEEE J. Solid State Circuits, February, 2023
Energy-efficient Task Adaptation for NLP Edge Inference Leveraging Heterogeneous Memory Architectures.
CoRR, 2023
2022
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators.
IEEE J. Solid State Circuits, 2022
NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
9.8 A 25mm<sup>2</sup> SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33<sup>rd</sup> Hot Chips Symposium - August 22-24, 2021.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
2020
IEEE Micro, 2020
CoRR, 2020
A 3mm<sup>2</sup> Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Hot Chips 32 Symposium, 2020
2019
MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge.
IEEE Micro, 2019
A 16nm 25mm<sup>2</sup> SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2012
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012