Marco Cusmai

According to our database1, Marco Cusmai authored at least 8 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels.
IEEE J. Solid State Circuits, 2023

2022
A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2011
A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

2010
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
IEEE J. Solid State Circuits, 2010

A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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