Marco Ceriani

Orcid: 0000-0002-4498-5863

According to our database¹, Marco Ceriani authored at least 8 papers between 2008 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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2017

Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

2015

Exploring architectural support for applications with irregular memory patterns on distributed manycore systems.

[BibT_eX]

[DOI]

Marco Ceriani

PhD thesis, 2015

2013

Prototyping hardware support for irregular applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013

Exploring manycore multinode systems for irregular applications with FPGA prototyping.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Exploring hardware support for scaling irregular applications on multi-node multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2010

Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation.

[BibT_eX]

[DOI]

Proceedings of the Genetic and Evolutionary Computation Conference, 2010

2009

Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Marco Ceriani

Timeline

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