Marco A. Z. Alves

Orcid: 0000-0003-2440-2664

Affiliations:
  • Federal University of Paraná (UFPR), Department of Informatics, Curitiba, Brazil


According to our database1, Marco A. Z. Alves authored at least 84 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Online presence:

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Bibliography

2024
Quantitative Precipitation Estimation Using Weather Radar Data and Machine Learning Algorithms for the Southern Region of Brazil.
Remote. Sens., June, 2024

2023
On the performance limits of thread placement for array databases in non-uniform memory architectures.
Computing, May, 2023

#DeOlhoNosCorais: a polygonal annotated dataset to optimize coral monitoring (GitHub).
Dataset, May, 2023

#DeOlhoNosCorais: a polygonal annotated dataset to optimize coral monitoring (GitHub).
Dataset, January, 2023

Plug N' PIM: An integration strategy for Processing-in-Memory accelerators.
Integr., 2023

Improved Computation of Database Operators via Vector Processing Near-Data.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

Efficient Prequential AUC-PR Computation.
Proceedings of the International Conference on Machine Learning and Applications, 2023

NoGar: A Non-cooperative Game for Thread Pinning in Array Databases.
Proceedings of the Database and Expert Systems Applications, 2023

2022
#DeOlhoNosCorais: a pixel-wise annotated dataset to optimize coral monitoring (GitHub).
Dataset, December, 2022


Efficient Machine Learning execution with Near-Data Processing.
Microprocess. Microsystems, April, 2022

Terminator: A Secure Coprocessor to Accelerate Real-Time AntiViruses Using Inspection Breakpoints.
ACM Trans. Priv. Secur., 2022

Sim2PIM: A complete simulation framework for Processing-in-Memory.
J. Syst. Archit., 2022

Evaluation of Hash Join Operations Performance Executing on SDN Switches: A Cost Model Approach.
J. Inf. Data Manag., 2022

HEAVEN: A Hardware-Enhanced AntiVirus ENgine to accelerate real-time, signature-based malware detection.
Expert Syst. Appl., 2022

Vector In Memory Architecture for simple and high efficiency computing.
CoRR, 2022

AntiViruses under the microscope: A hands-on perspective.
Comput. Secur., 2022

SAPIVe: Simple AVX to PIM Vectorizer.
Proceedings of the XII Brazilian Symposium on Computing Systems Engineering, 2022

Comparison of Different Adaptable Cache Bypassing Approaches.
Proceedings of the XII Brazilian Symposium on Computing Systems Engineering, 2022

Advancing Database System Operators with Near-Data Processing.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022

Advancing Near-Data Processing with Precise Exceptions and Efficient Data Fetching.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Video Decoder Improvements with Near-Data Speculative Motion Compensation Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Aggressive Performance Improvement on Processing-in-Memory Devices by Adopting Hugepages.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021
Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions.
Int. J. Parallel Program., 2021

Processamento Distribuído de Operações Hash Join em Switches Programáveis: Uma Análise via Modelo de Custo.
Proceedings of the 36th Brazilian Symposium on Databases, 2021

Performance Analysis of Array Database Systems in Non-Uniform Memory Architecture.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Machine Learning Migration for Efficient Near-Data Processing.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Towards the Overcome of Performance Pitfalls in Data Stream Mining Tools.
Proceedings of the International Joint Conference on Neural Networks, 2021

2020
The self modifying code (SMC)-aware processor (SAP): a security look on architectural impact and support.
J. Comput. Virol. Hacking Tech., 2020

Freezing time emulating new and faster devices with virtual machines.
CCF Trans. High Perform. Comput., 2020

Near-Memory & In-Memory Detection of Fileless Malware.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

2019
Database Processing-in-Memory: An Experimental Study.
Proc. VLDB Endow., 2019

A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation.
Microprocess. Microsystems, 2019

Towards providing middleware-level proactive resource reorganisation for elastic HPC applications in the cloud.
Int. J. Grid Util. Comput., 2019

Trace-driven and processing time extensions for Noxim simulator.
Des. Autom. Embed. Syst., 2019

Artigo Visão: Processamento de Banco de Dados em Memória.
Proceedings of the 34th Brazilian Symposium on Databases, 2019

Skipping CNN Convolutions Through Efficient Memoization.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

The AV says: Your Hardware Definitions Were Updated!
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

Multi-phased Task Placement of HPC Applications in the Cloud.
Proceedings of the 18th International Symposium on Parallel and Distributed Computing, 2019

Database Processing-in-Memory: A Vision.
Proceedings of the Database and Expert Systems Applications, 2019

A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Evaluating Cache Line Behavior Predictors for Energy Efficient Processors.
Proceedings of the High Performance Computing Systems - 19th Symposium, 2018

Introducing Drowsy Technique to Cache Line Usage Predictors.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Near-Data Filters: Taking Another Brick from the Memory Wall.
Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2018

Evaluating Dead Line Predictors Efficiency with Drowsy Technique.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Freezing Time: A New Approach for Emulating Fast Storage Devices Using VM.
Proceedings of the 26th IEEE International Symposium on Modeling, 2018

An Elastic Multi-Core Allocation Mechanism for Database Systems.
Proceedings of the 34th IEEE International Conference on Data Engineering, 2018

Exploring IoT platform with technologically agnostic processing-in-memory framework.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

HIPE: HMC instruction predication extension applied on database processing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Processing in 3D memories to speed up operations on complex data structures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design space exploration for PIM architectures in 3D-stacked memories.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Affinity-Based Thread and Data Mapping in Shared Memory Systems.
ACM Comput. Surv., 2017

Trace-Driven Extension for Noxim Simulator.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Operand size reconfiguration for big data processing in memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimizing memory affinity with a hybrid compiler/OS approach.
Proceedings of the Computing Frontiers Conference, 2017

NIM: An HMC-Based Machine for Neuron Computation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Kernel-Based Thread and Data Mapping for Improved Memory Affinity.
IEEE Trans. Parallel Distributed Syst., 2016

A dynamic block-level execution profiler.
Parallel Comput., 2016

LAPT: A locality-aware page table for thread and data mapping.
Parallel Comput., 2016

Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Communication in Shared Memory: Concepts, Definitions, and Efficient Detection.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Large vector extensions inside the HMC.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Reconfigurable Vector Extensions inside the DRAM.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Opportunities and Challenges of Performing Vector Operations inside the DRAM.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

HMC and DDR Performance Trade-offs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

SiNUCA: A Validated Micro-Architecture Simulator.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems.
Proceedings of the Euro-Par 2015: Parallel Processing, 2015

Saving memory movements through vector processing in the DRAM.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols.
J. Parallel Distributed Comput., 2014

Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Optimizing Memory Locality Using a Locality-Aware Page Table.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Energy Efficient Last Level Caches via Last Read/Write Prediction.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

2012
Memory-aware Thread and Data Mapping for Hierarchical Multi-core Platforms.
Int. J. Netw. Comput., 2012

Energy Savings via Dead Sub-Block Prediction.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

2011
High Latency and Contention on Shared L2-Cache for Many-Core Architectures.
Parallel Process. Lett., 2011

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfigurable Comput., 2011

Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Impact of Parallel Workloads on NoC Architecture Design.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

TLP and ILP exploitation through a reconfigurable multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

2009
Performance Evaluation of NoC Architectures for Parallel Workloads.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Design of Interleaved Multithreading for Network Processors on Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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