Márcio Eduardo Kreutz

Orcid: 0000-0002-5684-7310

According to our database1, Márcio Eduardo Kreutz authored at least 51 papers between 1999 and 2024.

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Bibliography

2024
A Parity-Based Dual Modular Redundancy Approach for the Reliability of Data Transmission in Nanosatellite's Onboard Processing.
IEEE Access, 2024

2023
Development a Low-Cost Wireless Smart Meter with Power Quality Measurement for Smart Grid Applications.
Sensors, August, 2023

Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chip.
Des. Autom. Embed. Syst., June, 2023

Analysis of Electrical Signals by Machine Learning for Classification of Individualized Electronics on the Internet of Smart Grid Things (IoSGT) architecture.
J. Internet Serv. Appl., January, 2023

Predictive Fraud Detection: An Intelligent Method for Internet of Smart Grid Things Systems.
J. Internet Serv. Appl., January, 2023

2021
Using Machine Learning to Estimate Latency and Delivered Packets in Hybrids NoCs.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

2020
A simultaneous multithreading processor architecture with predictable timing behavior.
Des. Autom. Embed. Syst., 2020

A Routing based Genetic Algorithm for Task Mapping on MPSoC.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

Mapping Wired Links in a Hybrid Wired-Wireless Network-on-Chip.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

Machine Learning Based Seismic Region Classification.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

2019
An investigation of latency prediction for NoC-based communication architectures using machine learning techniques.
J. Supercomput., 2019

<i>RedScarf</i>: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip.
J. Syst. Archit., 2019

Using SDN Strategies to Improve Resource Management On a NoC.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Optimizing an Architecture with Software Pipelining Strategies.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Communication Latency Evaluation on a Software-Defined Network-on-Chip.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

Generation of Application Specific Fault Tolerant Irregular NoC Topologies Using Tabu Search.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

2018
A Coarse-Grained Reconfigurable Architecture for a PRET Machine.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

2016
Design Space Exploration Using UTNoCs and Genetic Algorithm.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016

A Runtime Mapping Algorithm to Tolerate Permanent Faults in a CGRA.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016

2015
Enabling NoC Performance Improvement Using a Fault Tolerance Mechanism.
Proceedings of the 2015 Brazilian Symposium on Computing Systems Engineering, 2015

Towards Formalized Model-Based Requirements for a Seamless Design Approach in Safety-Critical Systems Development.
Proceedings of the 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2015

Performance evaluation of hierarchical NoC topologies for stacked 3D ICs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

2014
Adaptive multiple switching strategy toward an ideal NoC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A NOC closed-loop performance monitor and adapter.
Microprocess. Microsystems, 2013

An Experimental Evaluation of Combination of Features on the IPNoSys.
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
A LLVM Based Development Environment for Embedded Systems Software Targeting the RISCO Processor.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

SCProcessor Builder: A Tool to Create and Simulate Processors in SystemC.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

H.264/AVC motion estimation on FPGAs and GPUs: A comparative study.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Reconfigurable Routers for Low Power and High Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2011

DDR SDRAM Memory Controller for Digital TV Decoders.
Proceedings of the Brazilian Symposium on Computing System Engineering, 2011

2010
Exploring memory organization in virtual MP-SoC platforms.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Monitor-adapter coupling for NOC performance tuning.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

2009
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Adaptive router architecture based on traffic behavior observability.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

NoC Power Optimization Using a Reconfigurable Router.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2007
Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm Application.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2005
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Models for Embedded Application Mapping onto NoCs: Timing Analysis.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Energy and latency evaluation of NoC topologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design space exploration on heterogeneous network-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
RASoC: A Router Soft-Core for Networks-on-Chip.
Proceedings of the 2004 Design, 2004

2003
The Impact of NoC Reuse on the Testing of Core-based Systems.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002
A Study on Communication Issues for Systems-on-Chip.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Low-Power Control Architecture for Embedded Processors.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

2001
Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S.
RITA, 2001

Communication Architectures for System-on-Chip.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
A Design Methodology for Embedded Systems based on Multiple Processors.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

System Synthesis for Multiprocessor Embedded Applications.
Proceedings of the 2000 Design, 2000

1999
Object-Oriented Modeling and Co-Simulation of Embedded Systems.
Proceedings of the VLSI: Systems on a Chip, 1999


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