Marcin Rogawski

According to our database, Marcin Rogawski authored at least 16 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off.

Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2014

ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption.

Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik

IACR Cryptol. ePrint Arch., 2014

A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs.

Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl.

Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol

Microprocess. Microsystems, 2013

2012

Security margin evaluation of SHA-3 contest finalists through SAT-based attacks.

Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny

IACR Cryptol. ePrint Arch., 2012

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs.

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, Malik Umar Sharif

IACR Cryptol. ePrint Arch., 2012

A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl.

Marcin Rogawski, Kris Gaj

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Groestl Tweaks and their Effect on FPGA Results.

Marcin Rogawski, Kris Gaj

IACR Cryptol. ePrint Arch., 2011

Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs.

Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates.

Rabia Shahid, Malik Umar Sharif, Marcin Rogawski, Kris Gaj

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.

Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010

Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve.

Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi, Marcin Rogawski

IEEE Trans. Computers, 2010

Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.

Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj

IACR Cryptol. ePrint Arch., 2010

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs.

Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski

Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

2003

Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices.

Marcin Rogawski

IACR Cryptol. ePrint Arch., 2003