Marcin Jeske

According to our database, Marcin Jeske authored at least 6 papers between 2000 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Substrate noise modeling in early floorplanning of MS-SOCs.

Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Substrate noise optimization in early floorplanning for mixed signal SOCs.

Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Substrate noise-aware floorplanning for mixed-signal SOCs.

Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Integrated floorplanning with buffer/channel insertion for bus-based designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.

Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2000

Disjunctive Decomposition of Switching Functions Using Symmetry Information.

Malgorzata Chrzanowska-Jeske, Wei Wang, Jing Xia, Marcin Jeske

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000