Marcelo Lubaszewski

According to our database1, Marcelo Lubaszewski authored at least 134 papers between 1992 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal Circuits.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

2022
Evaluating Fault Coverage of Structural and Specification-based Tests Obtained With a Low-Cost Analog TPG Tool.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

2020
A Highly Reliable Wearable Device for Fall Detection.
Proceedings of the IEEE Latin-American Test Symposium, 2020

2016
Successful prototyping of complex integrated circuits with focused ion beam.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2015
Exploring design diversity redundancy to improve resilience in mixed-signal systems.
Microelectron. Reliab., 2015

Low power, high-sensitivity clock recovery circuit for LF/HF RFID applications.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A low-power RFID enabled temperature sensor for cold chain management.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A low-power RF/analog front-end architecture for LF passive RFID tags with dynamic power sensing.
Proceedings of the IEEE International Conference on RFID, 2014

A power management system architecture for LF passive RFID tags.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Determining the test sources/sinks for NoC TAMs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluating the scalability of test buses.
Proceedings of the 2013 International Symposium on System on Chip, 2013

2012
Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiers.
Proceedings of the 13th Latin American Test Workshop, 2012

Low pin count DfT technique for RFID ICs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Contributions to the evaluation of ensembles of combinational logic gates.
Microelectron. J., 2011

Improving the yield of NoC-based systems through fault diagnosis and adaptive routing.
J. Parallel Distributed Comput., 2011

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.
J. Parallel Distributed Comput., 2011

Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.
J. Electron. Test., 2011

Fault Detection, Diagnosis and Prediction in Electrical Valves Using Self-Organizing Maps.
J. Electron. Test., 2011

Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Investigating the effects of transient faults in Programmable Capacitor Arrays.
Proceedings of the 12th Latin American Test Workshop, 2011

Evaluating energy consumption of homogeneous MPSoCs using spare tiles.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A broad strategy to detect crosstalk faults in network-on-chip interconnects.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Evaluating the effectiveness of a mixed-signal TMR scheme based on design diversity.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Concurrent test of Network-on-Chip interconnects and routers.
Proceedings of the 11th Latin American Test Workshop, 2010

Fault prediction in electrical valves using temporal Kohonen maps.
Proceedings of the 11th Latin American Test Workshop, 2010

Diversity TMR: Proof of concept in a mixed-signal case.
Proceedings of the 11th Latin American Test Workshop, 2010

Efficiently using data splitting and retransmission to tolerate faults in networks-on-chip interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Radiation effects on programmable analog devices and mitigation techniques.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy.
Proceedings of the 15th European Test Symposium, 2010

2009
Design of an embedded system for the proactive maintenance of electrical valves.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Resource-and-time-aware test strategy for configurable quaternary logic blocks.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Diagnosis of interconnect shorts in mesh NoCs.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors.
Proceedings of the 10th Latin American Test Workshop, 2009

NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time.
Proceedings of the 10th Latin American Test Workshop, 2009

Efficient Test Circuit to Qualify Logic Cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop.
VLSI Design, 2008

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers, 2008

A novel AES cryptographic core highly resistant to differential power analysis attacks.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A fault-tolerant, DFA-resistant AES core.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Comput. Digit. Tech., 2007

Guest Editorial.
J. Electron. Test., 2007

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.
J. Electron. Test., 2007

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Redefining and testing interconnect faults in Mesh NoCs.
Proceedings of the 2007 IEEE International Test Conference, 2007

Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Functional Test of Field Programmable Analog Arrays.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A cryptography core tolerant to DFA fault attacks.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Using a software testing technique to identify registers for partial scan implementation.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 11th European Test Symposium, 2006

2005
Built-in self-test of global interconnects of field programmable analog arrays.
Microelectron. J., 2005

Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.
J. Electron. Test., 2005

A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.
J. Electron. Test., 2005

Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A constraint-based solution for on-line testing of processors embedded in real-time applications.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

A scalable test strategy for network-on-chip routers.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
Proceedings of the 2005 Design, 2005

2004
Reusing an on-chip network for the test of core-based systems.
ACM Trans. Design Autom. Electr. Syst., 2004

A New FPGA for DSP Applications Integrating BIST Capabilities.
J. Electron. Test., 2004

Searching for Global Test Costs Optimization in Core-Based Systems.
J. Electron. Test., 2004

An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Reducing test time with processor reuse in network-on-chip based systems.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Test and Design-for-Test of Mixed-Signal Integrated Circuits.
Proceedings of the Information Technology, Selected Tutorials, 2004

2003
The SigmaDelta-BIST Method Applied to Analog Filters.
J. Electron. Test., 2003

The Impact of NoC Reuse on the Testing of Core-based Systems.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

SIFU! - A Didactic Stuck-at Fault Simulator.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Designing for Test Analog Signal Processors for MEMS-Based Inertial Sensors.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Power-aware NoC Reuse on the Testing of Core-based Systems.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Testability Properties of BDDs.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Generic and Detailed Search for TAM Definition in Core-Based Systems.
Proceedings of the 3rd Latin American Test Workshop, 2002

State Model Approach for Analog Fault Modeling.
Proceedings of the 3rd Latin American Test Workshop, 2002

Designing for Test Butterworth and Chebyshev Low-Pass Filters of Any Order.
Proceedings of the 3rd Latin American Test Workshop, 2002

Estimating Static Parameters of A-to-D Converters from Spectral Analysis.
Proceedings of the 3rd Latin American Test Workshop, 2002

Test Planning and Design Space Exploration in a Core-Based Environment.
Proceedings of the 2002 Design, 2002

2001
Concepção de Circuitos e Sistemas Integrados.
RITA, 2001

Guest Editorial.
J. Electron. Test., 2001

Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.
J. Electron. Test., 2001

Fault Models and Test Generation for OpAmp Circuits - The FFM.
J. Electron. Test., 2001

A BIST Procedure for Analog Mixers in Software Radio.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

An Analog-based Approach for MEMS Testing.
Proceedings of the 2nd Latin American Test Workshop, 2001

A Test Method for a Broad Class of DSP Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001

The Sigma-Delta-Bist Method Applied to Linear Analog Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001

Filter Sensitivity Analysis Using the TRAM.
Proceedings of the 2nd Latin American Test Workshop, 2001

Designing Testable Networks for Transfer Function Realization.
Proceedings of the 2nd Latin American Test Workshop, 2001

Built-in Test of Analog Non-Linear Circuits in a SOC Environment.
Proceedings of the SOC Design Methodologies, 2001

2000
Design of self-checking fully differential circuits and boards.
IEEE Trans. Very Large Scale Integr. Syst., 2000

A new adaptive analog test and diagnosis system.
IEEE Trans. Instrum. Meas., 2000

Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Testability Properties of Vertex Precedent BDDs.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Designing a Radiation Hardened 8051-Like Micro-Controller.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Fault Models and Compact Test Vectors for MOS OpAmp circuits.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing.
Proceedings of the 1st Latin American Test Workshop, 2000

Implementing a Self-Checking PROFIBUS Slave.
Proceedings of the 1st Latin American Test Workshop, 2000

Synthesis of a 8051-Like Microcontroller Tolerant to Transient Faults.
Proceedings of the 1st Latin American Test Workshop, 2000

On the Temperature Dependencies of Analog BIST.
Proceedings of the 1st Latin American Test Workshop, 2000

Using Reconfigurability Features to Break Down Test Costs: a Case Study.
Proceedings of the 1st Latin American Test Workshop, 2000

The Use of Macromodels on Op-Amp Circuits Fault Modeling.
Proceedings of the 1st Latin American Test Workshop, 2000

Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis Method.
Proceedings of the 1st Latin American Test Workshop, 2000

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.
Proceedings of the 2000 Design, 2000

TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Design and Test of MEMs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Fault modeling of suspended thermal MEMS.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.
Proceedings of the 1999 Design, 1999

1998
A Reliable Fail-Safe System.
IEEE Trans. Computers, 1998

Thermal Monitoring of Self-Checking Systems.
J. Electron. Test., 1998

Testing MEMS.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Microsystems Testing: an Approach and Open Problems.
Proceedings of the 1998 Design, 1998

An Approach to the On-Line Testing of Operational Amplifiers.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Bridging the Gap between Microelectronics and Micromechanics Testing.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
A CAT Tool for Frequency-domain Testing and Diagnosis on Analog.
J. Braz. Comput. Soc., 1997

1996
Unified built-in self-test for fully differential analog circuits.
J. Electron. Test., 1996

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.
J. Electron. Test., 1996

Design of high-performance band-pass sigma-delta modulator with concurrent error detection.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

ABILBO: Analog BuILt-in Block Observer.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

Thermal Monitoring Of Safety-Critical Integrated Systems.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Analog checkers with absolute and relative tolerances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Frequency-based BIST for analog circuit testin.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Mixed-signal circuits and boards for high safety applications.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Designing self-exercising analogue checkers.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Built-in self-test and fault diagnosis of fully differential analogue circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
On the Design of Self-Checking Boundary Scannable Boards.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992


  Loading...