Marcelo Lubaszewski
According to our database1,
Marcelo Lubaszewski
authored at least 134 papers
between 1992 and 2023.
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Bibliography
2023
Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal Circuits.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
2022
Evaluating Fault Coverage of Structural and Specification-based Tests Obtained With a Low-Cost Analog TPG Tool.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
2016
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
2015
Microelectron. Reliab., 2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
A low-power RF/analog front-end architecture for LF passive RFID tags with dynamic power sensing.
Proceedings of the IEEE International Conference on RFID, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
2013
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
2012
Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiers.
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Microelectron. J., 2011
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing.
J. Parallel Distributed Comput., 2011
J. Parallel Distributed Comput., 2011
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.
J. Electron. Test., 2011
Fault Detection, Diagnosis and Prediction in Electrical Valves Using Self-Organizing Maps.
J. Electron. Test., 2011
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Efficiently using data splitting and retransmission to tolerate faults in networks-on-chip interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy.
Proceedings of the 15th European Test Symposium, 2010
2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors.
Proceedings of the 10th Latin American Test Workshop, 2009
NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time.
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop.
VLSI Design, 2008
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers, 2008
A novel AES cryptographic core highly resistant to differential power analysis attacks.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Comput. Digit. Tech., 2007
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.
J. Electron. Test., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Using a software testing technique to identify registers for partial scan implementation.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 11th European Test Symposium, 2006
2005
Microelectron. J., 2005
J. Electron. Test., 2005
J. Electron. Test., 2005
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
A constraint-based solution for on-line testing of processors embedded in real-time applications.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
Proceedings of the 2005 Design, 2005
2004
ACM Trans. Design Autom. Electr. Syst., 2004
J. Electron. Test., 2004
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Information Technology, Selected Tutorials, 2004
2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Generic and Detailed Search for TAM Definition in Core-Based Systems.
Proceedings of the 3rd Latin American Test Workshop, 2002
State Model Approach for Analog Fault Modeling.
Proceedings of the 3rd Latin American Test Workshop, 2002
Designing for Test Butterworth and Chebyshev Low-Pass Filters of Any Order.
Proceedings of the 3rd Latin American Test Workshop, 2002
Estimating Static Parameters of A-to-D Converters from Spectral Analysis.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the 2002 Design, 2002
2001
Concepção de Circuitos e Sistemas Integrados.
RITA, 2001
J. Electron. Test., 2001
J. Electron. Test., 2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
An Analog-based Approach for MEMS Testing.
Proceedings of the 2nd Latin American Test Workshop, 2001
A Test Method for a Broad Class of DSP Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001
The Sigma-Delta-Bist Method Applied to Linear Analog Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001
Filter Sensitivity Analysis Using the TRAM.
Proceedings of the 2nd Latin American Test Workshop, 2001
Designing Testable Networks for Transfer Function Realization.
Proceedings of the 2nd Latin American Test Workshop, 2001
Built-in Test of Analog Non-Linear Circuits in a SOC Environment.
Proceedings of the SOC Design Methodologies, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing.
Proceedings of the 1st Latin American Test Workshop, 2000
Implementing a Self-Checking PROFIBUS Slave.
Proceedings of the 1st Latin American Test Workshop, 2000
Synthesis of a 8051-Like Microcontroller Tolerant to Transient Faults.
Proceedings of the 1st Latin American Test Workshop, 2000
On the Temperature Dependencies of Analog BIST.
Proceedings of the 1st Latin American Test Workshop, 2000
Using Reconfigurability Features to Break Down Test Costs: a Case Study.
Proceedings of the 1st Latin American Test Workshop, 2000
The Use of Macromodels on Op-Amp Circuits Fault Modeling.
Proceedings of the 1st Latin American Test Workshop, 2000
Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis Method.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the 1999 Design, 1999
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
A CAT Tool for Frequency-domain Testing and Diagnosis on Analog.
J. Braz. Comput. Soc., 1997
1996
J. Electron. Test., 1996
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.
J. Electron. Test., 1996
Design of high-performance band-pass sigma-delta modulator with concurrent error detection.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
1993
Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992