Marcelo de Souza Moraes

According to our database, Marcelo de Souza Moraes authored at least 5 papers between 2005 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Low pin count DfT technique for RFID ICs.

Marcelo de Souza Moraes, Marcos Barcellos Hervé, Marcelo Lubaszewski

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.

Marcos Barcellos Hervé, Marcelo de Souza Moraes, Pedro Almeida, Marcelo Lubaszewski, Fernanda Lima Kastensmidt, Érika F. Cota

J. Electron. Test., 2011

2006

Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.

Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes

Proceedings of the IFIP VLSI-SoC 2006, 2006

Using a software testing technique to identify registers for partial scan implementation.

Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

2005

A constraint-based solution for on-line testing of processors embedded in real-time applications.

Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005