Marcelo Brandalero
Orcid: 0000-0002-0012-7023
According to our database1,
Marcelo Brandalero
authored at least 42 papers
between 2013 and 2023.
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Bibliography
2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
2022
Microprocess. Microsystems, October, 2022
Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy Using a Novel Data Augmentation Method.
IEEE Trans. Emerg. Top. Comput., 2022
Reduced Precision DWC: An Efficient Hardening Strategy for Mixed-Precision Architectures.
IEEE Trans. Computers, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Computers, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
2020
Proceedings of the Signal Processing: Algorithms, 2020
Proceedings of the Signal Processing: Algorithms, 2020
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
(Special Topic Submission) Enabling Domain-Specific Architectures with an Open-Source Soft-Core GPGPU.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020
A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
Predicting performance in multi-core systems with shared reconfigurable accelerators.
J. Syst. Archit., 2019
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Sci. Comput. Program., 2018
Microprocess. Microsystems, 2018
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism.
Des. Autom. Embed. Syst., 2016
The Potential of Accelerating Image-Processing Applications by Using Approximate Function Reuse.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016
2015
2014
Potential of Using a Reconfigurable System on a Superscalar Core for ILP Improvements.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014
2013
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013