Marcelo Antonio Pavanello

According to our database, Marcelo Antonio Pavanello authored at least 20 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Electrical Characterization of nMOSFETs from a 180 nm Commercial Technology at Low Temperatures.

Jessé de Oliveira, Marcelo Antonio Pavanello, Michelly de Souza

Proceedings of the 21st International Conference on Electrical Engineering, 2024

Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires.

Giovanni Almeida Matos, Jaime CalÇade Rodrigues, Michelly de Souza, Mikaël Cassé, Sylvain Barraud, Olivier Faynot, Marcelo Antonio Pavanello

Proceedings of the 21st International Conference on Electrical Engineering, 2024

2021

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors.

Michelly de Souza, Sylvain Barraud, Mikaël Cassé, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019

Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors.

Renan Trevisoli, Rodrigo Trevisoli Doria, Sylvain Barraud, Marcelo Antonio Pavanello

Proceedings of the 49th European Solid-State Device Research Conference, 2019

FOSS EKV2.6 Verilog-A Compact MOSFET Model.

Wladek Grabinski, Ahmed Abo-Elhadid, Marek Mierzwinski, Laurent Lemaitre, Mike Brinson, Christophe Lallement, Jean-Michel Sallese, Sadayuki Yoshitomi, Paul Malisse, Henri Oguey, Stefan Cserveny, Marcelo Antonio Pavanello, Christian C. Enz, François Krummenacher, Eric A. Vittoz, Michelly de Souza, Daniel Tomaszewski, Jolanta Malesinska, Grzegorz Gluszko, Matthias Bucher, Nikolaos Makris, Aristeidis Nikolaou

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K.

Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello

Microelectron. Reliab., 2017

A new method for junctionless transistors parameters extraction.

Renan Trevisoli Doria, Rodrigo Trevisoli Doria, Michelly de Souza, Marcelo Antonio Pavanello, Sylvain Barraud

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Drain current model for short-channel triple gate junctionless nanowire transistors.

Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello

Microelectron. Reliab., 2016

Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors.

Magali Estrada, M. Rivas, Ivan Garduño, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello, Israel Mejia, M. A. Quevedo-Lopez

Microelectron. Reliab., 2016

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors.

Rafael Assalti, Lígia Martins d'Oliveira, Marcelo Antonio Pavanello, Denis Flandre, Michelly de Souza

IET Circuits Devices Syst., 2016

Analog performance of strained SOI nanowires down to 10K.

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2013

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs.

Michelly de Souza, Bruna Cardoso Paz, Denis Flandre, Marcelo Antonio Pavanello

Microelectron. Reliab., 2013

2012

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices.

Renan Trevisoli Doria, João Antonio Martino, Eddy Simoen, Cor Claeys, Marcelo Antonio Pavanello

Microelectron. Reliab., 2012

2011

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances.

Denise C. Lugo Muñoz, Juan Muci, Adelmo Ortiz-Conde, Francisco J. García-Sánchez, Michelly de Souza, Marcelo Antonio Pavanello

Microelectron. Reliab., 2011

2008

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation.

Rodrigo Trevisoli Doria, Antonio Cerdeira, Jean-Pierre Raskin, Denis Flandre, Marcelo Antonio Pavanello

Microelectron. J., 2008

2006

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications.

Marcelo Antonio Pavanello, Paula Ghedini Der Agopian, João Antonio Martino, Denis Flandre

Microelectron. J., 2006

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS.

Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre

Microelectron. J., 2006

Evaluation of graded-channel SOI MOSFET operation at high temperatures.

Milene Galeti, Marcelo Antonio Pavanello, João Antonio Martino

Microelectron. J., 2006

2003

Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.

Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Stephane Adriaensen, Denis Flandre

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2001

Analog Circuit Design Using Graded-Channel SOI NMOSFETS.

Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001