Marcello Barbirotta

According to our database, Marcello Barbirotta authored at least 20 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme.

Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri

IEEE Trans. Computers, July, 2024

Enhancing Fault Tolerance in High-Performance Computing: A Real Hardware Case Study on a RISC-V Vector Processing Unit.

Marcello Barbirotta, Francesco Minervini, Carlos Rojas Morales, Adrián Cristal, Osman S. Unsal, Mauro Olivieri

IEEE Open J. Comput. Soc., 2024

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection.

Francesco Vigli, Marcello Barbirotta, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri

IEEE Access, 2024

Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems.

Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri

IEEE Access, 2024

Exploring Variable Latency Dividers in Vector Hardware Accelerators.

Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri

Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024

AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs.

Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri

Proceedings of the International Joint Conference on Neural Networks, 2024

Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation.

Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor.

Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023

Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor.

Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri

Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach.

Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects.

Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.

Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.

Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri

IEEE Access, 2022

Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration.

Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor.

Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators.

Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool.

Silvia Casalinuovo, Alessio Buzzin, Antonio Mastrandrea, Ivan Mazzetta, Marcello Barbirotta, Lorenzo Iannascoli, Augusto Nascetti, Giampiero de Cesare, Donatella Puglisi, Domenico Caputo

Proceedings of the Sensors and Microsystems, 2022

2021

A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.

Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

ADMM Consensus for Deep LSTM Networks.

Antonello Rosato, Federico Succetti, Marcello Barbirotta, Massimo Panella

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment.

Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020