Marcelino B. Santos
Orcid: 0000-0002-2091-1165
According to our database1,
Marcelino B. Santos
authored at least 97 papers
between 1992 and 2024.
Collaborative distances:
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Bibliography
2024
Integrated Demodulator for Manchester-Coded AM Signals with Clock Retrieval in US Applications.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
2023
Proceedings of the 19th International Conference on Synthesis, 2023
Delta-Sigma Control Loop For Energy-Efficient Electrical Stimulation with Arbitrary-Shape Stimuli.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
2022
Proceedings of the Universal Access in Human-Computer Interaction. Novel Design Approaches and Technologies, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2020
Proceedings of the Convergence of Artificial Intelligence and the Internet of Things, 2020
2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018
Low noise, high efficiency, segmented LCD drivers for ultra-low power applications in 22 nm FD-SOI.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2015
Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling.
J. Low Power Electron., 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
2014
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Microelectron. J., 2013
ActivIC: Design-Based Automatic Characterization of Mixed-Signal Integrated Circuits.
J. Low Power Electron., 2013
J. Electron. Test., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
J. Low Power Electron., 2012
IEEE Des. Test Comput., 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
2011
Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter.
J. Low Power Electron., 2011
On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications.
J. Low Power Electron., 2011
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications.
Proceedings of the 12th Latin American Test Workshop, 2011
ICT: Interface software for the characterization and test of mixed-signal power cores.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of EUROCON 2011, 2011
Proceedings of EUROCON 2011, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Low-sensitivity to process variations aging sensor for automotive safety-critical applications.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
J. Low Power Electron., 2009
J. Low Power Electron., 2009
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
IEEE Trans. Ind. Electron., 2008
J. Low Power Electron., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Adjustable low consumption circuit for monitorization of power source voltages in a SoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
BIST Architectures and Fault Emulation.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.
J. Electron. Test., 2005
Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
2004
J. Electron. Test., 2004
Comput. Artif. Intell., 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the 2003 Design, 2003
2002
J. Electron. Test., 2002
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System.
J. Electron. Test., 2002
On High-Quality, Low Energy BIST Preparation at RT-Level.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
J. Electron. Test., 2001
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
2000
Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-Chip.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the 5th European Test Workshop, 2000
1999
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 1999 Design, 1999
1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the conference on European design automation, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Test preparation methodology for high coverage of physical defects in CMOS digital ICs.
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Realistic Fault Analysis of CMOS Analog Building Blocks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Microprocess. Microprogramming, 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992