Marcel Merten
Orcid: 0000-0002-6654-6773
According to our database1,
Marcel Merten
authored at least 10 papers
between 2020 and 2024.
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Bibliography
2024
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024
2023
Proceedings of the Companion Proceedings of the Conference on Genetic and Evolutionary Computation, 2023
Proceedings of the IEEE European Test Symposium, 2023
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods.
Proceedings of the IEEE European Test Symposium, 2022
2021
Proceedings of the GECCO '21: Genetic and Evolutionary Computation Conference, 2021
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Proceedings of the GECCO '20: Genetic and Evolutionary Computation Conference, 2020