Marc Stöttinger
Orcid: 0000-0001-7970-3945
According to our database1,
Marc Stöttinger
authored at least 49 papers
between 2009 and 2024.
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Bibliography
2024
Proceedings of the 54. Jahrestagung der Gesellschaft für Informatik, 2024
Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Towards Private Deep Learning-Based Side-Channel Analysis Using Homomorphic Encryption - Opportunities and Limitations.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024
2023
Separating Oil and Vinegar with a Single Trace Side-Channel Assisted Kipnis-Shamir Attack on UOV.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Towards Private Deep Learning-based Side-Channel Analysis using Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023
2022
IACR Cryptol. ePrint Arch., 2022
Proceedings of the Selected Areas in Cryptography - 29th International Conference, 2022
Cyber Threat Observatory: Design and Evaluation of an Interactive Dashboard for Computer Emergency Response Teams.
Proceedings of the 30th European Conference on Information Systems, 2022
2021
CYWARN: Strategy and Technology Development for Cross-Platform Cyber Situational Awareness and Actor-Specific Cyber Threat Communication.
Proceedings of the Mensch und Computer 2021, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
Trouble at the CSIDH: Protecting CSIDH with Dummy-Operations against Fault Injection Attacks.
IACR Cryptol. ePrint Arch., 2020
2019
Proceedings of the 24th IEEE European Test Symposium, 2019
2018
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018
2016
Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
There ain't no plain key: A PUF based first-order side-channel resistant encryption construction.
Proceedings of the International Symposium on Integrated Circuits, 2016
2015
Support vector regression: exploiting machine learning techniques for leakage modeling.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015
2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014
2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective.
Proceedings of the Progress in Cryptology - INDOCRYPT 2013, 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Proceedings of the Workshop on Embedded Systems Security, 2013
AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework.
Proceedings of the Number Theory and Cryptography, 2013
2012
PhD thesis, 2012
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
Side-channel resistant AES architecture utilizing randomized composite field representations.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A New Difference Method for Side-Channel Analysis with High-Dimensional Leakage Models.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
2011
J. Cryptogr. Eng., 2011
How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010
2009
Proceedings of the Information, Security and Cryptology, 2009