Marc Stöttinger

Orcid: 0000-0001-7970-3945

According to our database1, Marc Stöttinger authored at least 49 papers between 2009 and 2024.

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Bibliography

2024
Shell we find it: A Shelly Smart Home Device Discovery Tool.
Proceedings of the 54. Jahrestagung der Gesellschaft für Informatik, 2024

Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Towards Private Deep Learning-Based Side-Channel Analysis Using Homomorphic Encryption - Opportunities and Limitations.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

2023
Separating Oil and Vinegar with a Single Trace Side-Channel Assisted Kipnis-Shamir Attack on UOV.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Towards Private Deep Learning-based Side-Channel Analysis using Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023

Separating Oil and Vinegar with a Single Trace.
IACR Cryptol. ePrint Arch., 2023

Voronoi Based Multidimensional Parameter Optimization for Fault Injection Attacks.
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023

Verified Value Chains, Innovation and Competition.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023

2022
Patient Zero and Patient Six: Zero-Value and Correlation Attacks on CSIDH and SIKE.
IACR Cryptol. ePrint Arch., 2022

Patient Zero & Patient Six: Zero-Value and Correlation Attacks on CSIDH and SIKE.
Proceedings of the Selected Areas in Cryptography - 29th International Conference, 2022

Cyber Threat Observatory: Design and Evaluation of an Interactive Dashboard for Computer Emergency Response Teams.
Proceedings of the 30th European Conference on Information Systems, 2022

2021
Verifying Post-Quantum Signatures in 8 kB of RAM.
IACR Cryptol. ePrint Arch., 2021

CYWARN: Strategy and Technology Development for Cross-Platform Cyber Situational Awareness and Actor-Specific Cyber Threat Communication.
Proceedings of the Mensch und Computer 2021, 2021

A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Post-Quantum Secure Architectures for Automotive Hardware Secure Modules.
IACR Cryptol. ePrint Arch., 2020

LMS vs XMSS: Comparison of Stateful Hash-Based Signature Schemes on ARM Cortex-M4.
IACR Cryptol. ePrint Arch., 2020

Trouble at the CSIDH: Protecting CSIDH with Dummy-Operations against Fault Injection Attacks.
IACR Cryptol. ePrint Arch., 2020

2019
Serialized lightweight SHA-3 FPGA implementations.
Microprocess. Microsystems, 2019

Security in Autonomous Systems.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Efficient Side-Channel Protections of ARX Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

2016
Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

There ain't no plain key: A PUF based first-order side-channel resistant encryption construction.
Proceedings of the International Symposium on Integrated Circuits, 2016

2015
Support vector regression: exploiting machine learning techniques for leakage modeling.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Evaluation Tools for Multivariate Side-Channel Analysis.
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015

2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014

Zero collision attack and its countermeasures on Residue Number System multipliers.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Constructive side-channel analysis for secure hardware design.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A signature based architecture for Trojan detection.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

Minimizing S-Boxes in Hardware by Utilizing Linear Transformations.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014

2013
Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective.
Proceedings of the Progress in Cryptology - INDOCRYPT 2013, 2013

TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Hardware trojan design and detection: a practical evaluation.
Proceedings of the Workshop on Embedded Systems Security, 2013

AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework.
Proceedings of the Number Theory and Cryptography, 2013

2012
Mutating runtime architectures as a countermeasure against power analysis attacks.
PhD thesis, 2012

An adaptable, modular, and autonomous side-channel vulnerability evaluator.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Side-channel resistant AES architecture utilizing randomized composite field representations.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Side channel analysis of the SHA-3 finalists.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Revealing side-channel issues of complex circuits by enhanced leakage models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A New Difference Method for Side-Channel Analysis with High-Dimensional Leakage Models.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

Butterfly-Attack on Skein's Modular Addition.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011
A simple power analysis attack on a McEliece cryptoprocessor.
J. Cryptogr. Eng., 2011

How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
A stochastic method for security evaluation of cryptographic FPGA implementations.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Virtualization within a Parallel Array of Homogeneous Processing Units.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
A Timing Attack against Patterson Algorithm in the McEliece PKC.
Proceedings of the Information, Security and Cryptology, 2009


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