Marc Riera

According to our database, Marc Riera authored at least 21 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

An energy-efficient near-data processing accelerator for DNNs to optimize memory accesses.

Bahareh Khabbazan, Mohammad Sabri, Marc Riera, Antonio González

J. Syst. Archit., 2025

2024

Exploiting beam search confidence for energy-efficient speech recognition.

Dennis Pinto, José-María Arnau, Marc Riera, José-Lorenzo Cruz, Antonio González

J. Supercomput., November, 2024

Mixture-of-Rookies: Saving DNN computations by predicting ReLU outputs.

Dennis Pinto, José-María Arnau, Marc Riera, José-Lorenzo Cruz, Antonio González

Microprocess. Microsystems, 2024

ARAS: An Adaptive Low-Cost ReRAM-Based Accelerator for DNNs.

Mohammad Sabri, Marc Riera, Antonio González

CoRR, 2024

ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNNs.

Mohammad Sabri Abrebekoh, Marc Riera Villanueva, Antonio González

Proceedings of the 53rd International Conference on Parallel Processing, 2024

Community-driven machine translation for the Catalan language at Softcatalà.

Xavi Ivars-Ribes, Jordi Mas, Marc Riera, Jaume Ortolà, Mikel Forcada, David Cànovas

Proceedings of the 25th Annual Conference of the European Association for Machine Translation (Volume 2), 2024

2023

An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses.

Bahareh Khabbazan, Marc Riera, Antonio González

CoRR, 2023

ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference.

Mohammad Sabri Abrebekoh, Marc Riera, Antonio González

CoRR, 2023

DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference.

Bahareh Khabbazan, Marc Riera, Antonio González

Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023

QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures.

Bahareh Khabbazan, Marc Riera, Antonio González

Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022

A Survey of Near-Data Processing Architectures for Neural Networks.

Mehdi Hassanpour, Marc Riera, Antonio González

Mach. Learn. Knowl. Extr., 2022

CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs.

Marc Riera, José-María Arnau, Antonio González

J. Syst. Archit., 2022

DNN pruning with principal component analysis and connection importance estimation.

Marc Riera, José-María Arnau, Antonio González

J. Syst. Archit., 2022

2020

Low-power accelerators for cognitive computing.

Marc Riera

PhD thesis, 2020

2019

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.

Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo

IEEE Trans. Computers, 2019

CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference.

Marc Riera, José-María Arnau, Antonio González

IEEE Micro, 2019

(Pen-) Ultimate DNN Pruning.

Marc Riera, José-María Arnau, Antonio González

CoRR, 2019

2018

The Dark Side of DNN Pruning.

Reza Yazdani, Marc Riera, José-María Arnau, Antonio González

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Computation Reuse in DNNs by Exploiting Input Similarity.

Marc Riera, José-María Arnau, Antonio González

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2016

Cross-layer system reliability assessment framework for hardware faults.

Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale

Proceedings of the 2016 IEEE International Test Conference, 2016

A detailed methodology to compute Soft Error Rates in advanced technologies.

Marc Riera, Ramon Canal, Jaume Abella, Antonio González

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016