Marc Riera
Orcid: 0000-0002-2768-5703
According to our database1,
Marc Riera
authored at least 15 papers
between 2016 and 2023.
Collaborative distances:
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Bibliography
2023
An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses.
CoRR, 2023
ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference.
CoRR, 2023
Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023
QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
Mach. Learn. Knowl. Extr., 2022
CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs.
J. Syst. Archit., 2022
J. Syst. Archit., 2022
2020
2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019
IEEE Micro, 2019
2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016