Marc Padilla

Orcid: 0000-0002-9432-6591

According to our database1, Marc Padilla authored at least 6 papers between 2010 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
Assessing the Temporal Stability of the Accuracy of a Time Series of Burned Area Products.
Remote. Sens., 2014

2011
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Rapid prototyping tools for FPGA designs: RapidSmith.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Using Hard Macros to Reduce FPGA Compilation Time.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010


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