Marc Boule

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2013

Test compaction techniques for assertion-based test generation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Efficient Data Encoding for Improving Fault Simulation Performance on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2010

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Defining and Providing Coverage for Assertion-Based Dynamic Verification.

[BibT_eX]

[DOI]

J. Electron. Test., 2010

2009

Airwolf-TG: A test generator for assertion-based dynamic verification.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

MYGEN: automata-based on-line test generator for assertion-based verification.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Automata-based assertion-checker synthesis of PSL properties.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Proving and disproving assertion rewrite rules with automated theorem provers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2007

Debug enhancements in assertion-checker generation.

[BibT_eX]

[DOI]

Jean-Samuel Chenard

IET Comput. Digit. Tech., 2007

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis.

[BibT_eX]

[DOI]

Jean-Samuel Chenard

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.

[BibT_eX]

[DOI]

Jean-Samuel Chenard

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

Incorporating Ef.cient Assertion Checkers into Hardware Emulation.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2002

An FPGA Move Generator for the Game of Chess.

[BibT_eX]

J. Int. Comput. Games Assoc., 2002

An FPGA based move generator for the game of chess.

[BibT_eX]

[DOI]