Marc Belleville
According to our database1,
Marc Belleville
authored at least 27 papers
between 2007 and 2017.
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Bibliography
2017
J. Low Power Electron., 2017
2016
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.
Microelectron. J., 2016
Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era.
ACM J. Emerg. Technol. Comput. Syst., 2016
2015
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
2014
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.
J. Low Power Electron., 2014
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
An efficient metric of setup time for pulsed flip-flops based on output transition time.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below.
J. Low Power Electron., 2012
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectron. J., 2011
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Microelectron. J., 2010
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.
J. Low Power Electron., 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
2009
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007