We stand with Ukraine  

Marc-André Daigneault

According to our database1, Marc-André Daigneault authored at least 10 papers between 2008 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
Automated Synthesis of Streaming Transfer Level Hardware Designs.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
ACM Trans. Reconfigurable Technol. Syst., 2018

2015
Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

2014
Fast description and synthesis of control-dominant circuits.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Comput. Electr. Eng., 2014

2013
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only).
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Synchronized-transfer-level design methodology applied to hardware matrix multiplication.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Raising the abstraction level of HDL for control-dominant applications.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration.
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
IEEE Trans. Instrum. Meas., 2011

2010
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).
[BibTeX]
[DOI]
Marc-André Daigneault
,
Jean-Pierre David
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2008
Application Specific Instruction set processor specialized for block motion estimation.
[BibTeX]
[DOI]
Marc-André Daigneault
,
J. M. Pierre Langlois
,
Jean-Pierre David
Proceedings of the 26th International Conference on Computer Design, 2008


  Loading...