Maoxiang Yi
Orcid: 0000-0002-5160-0933
According to our database1,
Maoxiang Yi
authored at least 42 papers
between 2005 and 2025.
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Bibliography
2025
Lightweight high-throughput true random number generator based on state switchable ring oscillator.
Integr., 2025
2024
Lightweight Hybrid Entropy Source True Random Number Generator Based on Jitter and Metastability.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
J. Electron. Test., June, 2024
IEICE Electron. Express, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., December, 2023
Integr., May, 2023
A dynamically reconfigurable entropy source circuit for high-throughput true random number generator.
Microelectron. J., March, 2023
Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern.
Microelectron. J., 2023
2022
Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A reconfigurable PUF structure with dual working modes based on entropy separation model.
Microelectron. J., 2022
Integr., 2022
J. Electron. Test., 2022
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
2021
Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator.
IEEE Trans. Very Large Scale Integr. Syst., 2021
High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A high reliability physically unclonable function based on multiple tunable ring oscillator.
Microelectron. J., 2021
Integr., 2021
2020
2019
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
2018
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS.
Proceedings of the 27th IEEE Asian Test Symposium, 2018
An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
J. Circuits Syst. Comput., 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
2016
Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect.
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
2015
A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.
IEICE Trans. Electron., 2015
NBTI-induced circuit aging optimization by protectability-aware gate replacement technique.
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015
2011
Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination.
Proceedings of the IEEE 10th International Conference on Trust, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009
2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005