Maohua Zhu

Orcid: 0000-0002-8914-9834

According to our database1, Maohua Zhu authored at least 12 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.
IEEE J. Solid State Circuits, 2020

fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Dynamic Sparse Graph for Efficient Deep Learning.
Proceedings of the 7th International Conference on Learning Representations, 2019

2018
Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training.
CoRR, 2018

2016
CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis.
CoRR, 2016

OpenCL caffe: Accelerating and enabling a cross platform machine learning framework.
Proceedings of the 4th International Workshop on OpenCL, 2016

2014
Implementation and evaluation of deep neural networks (DNN) on mainstream heterogeneous systems.
Proceedings of the Asia-Pacific Workshop on Systems, 2014

2012
A Polyhedral Modeling Based Source-to-Source Code Optimization Framework for GPGPU.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
Evaluating the potential of graphics processors for high performance embedded computing.
Proceedings of the Design, Automation and Test in Europe, 2011


  Loading...