Mao-Chih Hsia

According to our database, Mao-Chih Hsia authored at least 3 papers between 2011 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist.

Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu

Proceedings of the IEEE 25th International SOC Conference, 2012

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.

Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.

Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011