Manuel Jesús Bellido Díaz

According to our database, Manuel Jesús Bellido Díaz authored at least 26 papers between 1993 and 2012.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2012

Network Time Synchronization: A Full Hardware Approach.

Jorge Juan, Julian Viejo, Manuel J. Bellido

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2010

Design and implementation of a suitable core for on-chip long-term verification.

Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa

Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

2009

Efficient techniques and methodologies for embedded system design usign free hardware and open standards.

Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.

Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Design of a FFT/IFFT module as an IP core suitable for embedded systems.

Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz

Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

Static Power Consumption in CMOS Gates Using Independent Bodies.

David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.

Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos

Proceedings of the International Symposium on Industrial Embedded Systems, 2006

2005

Logic-Level Fast Current Simulation for Digital CMOS Circuits.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo

Proceedings of the Integrated Circuit and System Design, 2005

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.

Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo

Proceedings of the Integrated Circuit and System Design, 2005

2004

Signal Sampling Based Transition Modeling for Digital Gates Characterization.

Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa

Proceedings of the Integrated Circuit and System Design, 2004

2003

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.

David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán

Proceedings of the Integrated Circuit and System Design, 2003

Internode: Internal Node Logic Computational Model.

Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa

Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).

Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.

Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001

Gate-level simulation of CMOS circuits using the IDDM model.

Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

AUTODDM: automatic characterization tool for the delay degradation model.

Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Degradation Delay Model Extension to CMOS Gates.

Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design, 2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.

Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design, 2000

Inertial and degradation delay model for CMOS logic gates.

Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998

Efficient self-timed circuits based on weak NMOS-trees.

Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996

Multimedia System for Instruction and Learning Electronics.

P. Fortet, Manuel J. Bellido, Francisco Sivianes, A. V. Medina

Proceedings of the Computer Aided Learning and Instruction in Science and Engineering, 1996

1995

New CMOS VLSI linear self-timed architectures.

Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas

Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1993

A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.

Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Modeling of real bistables in VHDL.

Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas

Proceedings of the European Design Automation Conference 1993, 1993