Manuel Eggimann
Orcid: 0000-0001-8395-7585
According to our database1,
Manuel Eggimann
authored at least 20 papers
between 2018 and 2024.
Collaborative distances:
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Bibliography
2024
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine.
IEEE J. Solid State Circuits, July, 2024
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
IEEE J. Solid State Circuits, January, 2024
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Near-Memory Computing Architectures and Circuits for Ultra-Low Power Near-Sensor Processors.
PhD thesis, 2023
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
CoRR, 2023
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022
2021
A 5 μW Standard Cell Memory-Based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Sustain. Comput. Informatics Syst., 2021
TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition With Short Range Radars.
IEEE Internet Things J., 2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
HR-SAR-Net: A Deep Neural Network for Urban Scene Segmentation from High-Resolution SAR Data.
CoRR, 2019
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019
An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018