Manuel Delgado-Restituto
Orcid: 0000-0002-7707-0897Affiliations:
- University of Seville, Spain
According to our database1,
Manuel Delgado-Restituto
authored at least 72 papers
between 1993 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process.
Sensors, 2022
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
IEEE Trans. Biomed. Circuits Syst., 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
2020
A Sub- $\mu$ W Reconfigurable Front-End for Invasive Neural Recording That Exploits the Spectral Characteristics of the Wideband Neural Signal.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Biomed. Circuits Syst., 2020
2019
Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation.
IEEE Trans. Biomed. Circuits Syst., 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Hardware friendly algorithm for the calculation of phase synchronization between neural signals.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces.
IEEE Trans. Biomed. Circuits Syst., 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
In vivo measurements with a 64-channel extracellular neural recording integrated circuit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE J. Solid State Circuits, 2013
Int. J. Circuit Theory Appl., 2013
Int. J. Circuit Theory Appl., 2013
Far-field UHF remotely powered front-end for patient monitoring with wearable antenna.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
2012
IEEE Trans. Ind. Electron., 2012
A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression.
IEEE Trans. Biomed. Circuits Syst., 2012
IEEE J. Solid State Circuits, 2012
Int. J. Circuit Theory Appl., 2012
Int. J. Circuit Theory Appl., 2012
An RF-to-DC energy harvester for co-integration in a low-power 2.4 GHz transceiver frontend.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
An RF energy harvester with supply management for co-integration into a 2.4 GHz transceiver.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
2011
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Int. J. Circuit Theory Appl., 2009
Design constraints for the inductive power and data link of an implanted body sensor.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
Matrix Methods for the Dynamic Range Optimization of Continuous-Time G<sub>m</sub>- C Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE J. Solid State Circuits, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
Integr., 2003
2002
2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
1999
MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips.
J. VLSI Signal Process., 1999
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1995
Secure Communication Through Switched-Current Chaotic Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
J. Intell. Fuzzy Syst., 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Proceedings of the Chua's Circuit: A Paradigm for Chaos, 1993