Manu Perumkunnil Komalan
Orcid: 0000-0002-0029-6548
According to our database1,
Manu Perumkunnil Komalan
authored at least 27 papers
between 2013 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024
2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Proceedings of the 20th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2023
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
2022
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices.
ACM Trans. Embed. Comput. Syst., 2022
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021
Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Comput. Archit. Lett., 2020
2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
System Level Management of Hybrid Memory Systems ; Systeem niveau beheer van hybride geheugen systemen ; Gestión de jerarquías de memoria híbridas a nivel de sistema.
PhD thesis, 2017
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Design exploration of a NVM based hybrid instruction memory organization for embedded platforms.
Des. Autom. Embed. Syst., 2013