Manu Awasthi

Orcid: 0000-0002-5616-9679

Affiliations:
  • Ashoka University, Department of Computer science, Sonepat, India
  • Indian Institute of Technology, Gandhinagar, India
  • Samsung Semiconductor Inc, Milpitas, CA, USA
  • University of Utah, UT, USA (PhD 2014)


According to our database1, Manu Awasthi authored at least 42 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy.
ACM Trans. Archit. Code Optim., June, 2023

Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Analysis of Quantization Across DNN Accelerator Architecture Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
I/O Workload Management for All-Flash Datacenter Storage Systems Based on Total Cost of Ownership.
IEEE Trans. Big Data, 2022

A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms.
CoRR, 2022

Verifiable and Practical Compliance for Data Privacy Laws.
Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022

2021
Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy.
CoRR, 2021

2020
ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Prefetching in Hybrid Main Memory Systems.
Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020

2019
Memory Centric Characterization and Analysis of SPEC CPU2017 Suite.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

FAB: Framework for Analyzing Benchmarks.
Proceedings of the Companion of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

Efficacy of Statistical Sampling on Contemporary Workloads: The Case of SPEC CPU2017.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

2018
Docker Container Scheduler for I/O Intensive Applications Running on NVMe SSDs.
IEEE Trans. Multi Scale Comput. Syst., 2018

META: Memory Exploration Tool for Android Devices.
Proceedings of the 24th Annual International Conference on Mobile Computing and Networking, 2018

Exploring non-volatile main memory architectures for handheld devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Rack Level Scheduling for Containerized Workloads.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

Docker characterization on high performance SSDs.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016
Software-Defined Emulation Infrastructure for High Speed Storage.
Proceedings of the 9th ACM International on Systems and Storage Conference, 2016

DRAMScale: Mechanisms to Increase DRAM Capacity.
Proceedings of the Second International Symposium on Memory Systems, 2016

DRAMPersist: Making DRAM Systems Persistent.
Proceedings of the Second International Symposium on Memory Systems, 2016

Understanding performance of I/O intensive containerized applications for NVMe SSDs.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016

KOVA : A tool for kernel visualization and analysis.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016

FlexDrive: A Framework to Explore NVMe Storage Solutions.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

A Fresh Perspective on Total Cost of Ownership Models for Flash Storage in Datacenters.
Proceedings of the 2016 IEEE International Conference on Cloud Computing Technology and Science, 2016

2015
System-Level Characterization of Datacenter Applications.
Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering, Austin, TX, USA, January 31, 2015

Performance analysis of NVMe SSDs and their implication on real world databases.
Proceedings of the 8th ACM International Systems and Storage Conference, 2015

Performance Characterization of Hyperscale Applicationson on NVMe SSDs.
Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2015

Rethinking Design Metrics for Datacenter DRAM.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

2014
Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Codesign Approach.
PhD thesis, 2014

2012
Managing Data Placement in Memory Systems with Multiple Memory Controllers.
Int. J. Parallel Program., 2012

Efficient scrub mechanisms for error-prone emerging memories.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
Prediction Based DRAM Row-Buffer Management in the Many-Core Era.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Micro-pages: increasing DRAM efficiency with locality-aware data placement.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

Handling the problems and opportunities posed by multiple on-chip memory controllers.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Scalable and reliable communication for hardware transactional memory.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
Understanding the Impact of 3D Stacked Layouts on ILP.
J. Instr. Level Parallelism, 2007


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