Mansi Jhamb

According to our database, Mansi Jhamb authored at least 10 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application.

B. Jyothi, B. V. Ramana Reddy, Mansi Jhamb

Integr., 2025

2024

A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder.

Uma Sharma, Mansi Jhamb

Circuits Syst. Signal Process., December, 2024

2023

A 0.8-Volt 29.52-μW Current Mirror-Based OTA Design for Biomedical Applications.

Mansi Jhamb

J. Circuits Syst. Comput., September, 2023

Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.

Uma Sharma, Mansi Jhamb

Circuits Syst. Signal Process., May, 2023

2022

Ultra low power design of multi-valued logic circuit for binary interfaces.

Mansi Jhamb, Ratnesh Mohan

J. King Saud Univ. Comput. Inf. Sci., 2022

A Novel Design of Voltage and Temperature Resilient 9-T Domino Logic XOR /XNOR Cell.

Uma Sharma, Mansi Jhamb

Circuits Syst. Signal Process., 2022

2021

Ultra low power current mirror design with enhanced bandwidth.

Pritty, Mansi Jhamb

Microelectron. J., 2021

2019

A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design.

Mansi Jhamb, Vinod Kumar Khera, Piyush Pant, Hinduja Pudi

J. Circuits Syst. Comput., 2019

Pipelined adders for ultralow-power wearables.

Mansi Jhamb, Tejaswini Dhall, Tamish Verma, Hinduja Pudi

Turkish J. Electr. Eng. Comput. Sci., 2019

2017

A high level implementation and performance evaluation of level-I asynchronous cache on FPGA.

Mansi Jhamb, R. K. Sharma, A. K. Gupta

J. King Saud Univ. Comput. Inf. Sci., 2017