Manoranjan Pradhan

According to our database, Manoranjan Pradhan authored at least 6 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Improved Redundant Binary Adder Realization in FPGA.

Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan

J. Circuits Syst. Comput., 2021

2020

Fast signed multiplier using Vedic Nikhilam algorithm.

Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan

IET Circuits Devices Syst., 2020

2018

An efficient redundant binary adder with revised computational rules.

Ranjan Kumar Barik, Bandan Kumar Bhoi, Manoranjan Pradhan

Comput. Electr. Eng., 2018

2017

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation.

Ranjan Kumar Barik, Manoranjan Pradhan, Rutuparna Panda

J. Circuits Syst. Comput., 2017

Efficient ASIC and FPGA implementation of cube architecture.

Ranjan Kumar Barik, Manoranjan Pradhan

IET Comput. Digit. Tech., 2017

An Improved Conversion Circuit for Redundant Binary to Conventional Binary Representation.

Snigdha Subhadarshinee Tripathy, Ranjan Kumar Barik, Manoranjan Pradhan

Proceedings of the Computational Intelligence, Communications, and Business Analytics, 2017