Manoj Saxena

Orcid: 0000-0002-9368-4194

Affiliations:
  • University of Delhi, India


According to our database1, Manoj Saxena authored at least 19 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
Ohmic contacts to n-type SiC: Influence of Au and Ta intermediate layers.
Microelectron. J., 2024

2023
Secure digital image watermarking using memristor-based hyperchaotic circuit.
Vis. Comput., October, 2023

2022
Investigation of proton irradiated dual field plate AlGaN/GaN HEMTs: TCAD based assessment.
Microelectron. J., 2022

Interplay Between γ-Ray Irradiation and 3DEG for Dosimeter Applications.
IEEE Access, 2022

Implications of Field Plate HEMT Towards Power Performance at Microwave X - Band.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Investigation of Traps in AlGaN/GaN HEMT Epitaxial Structure Using Conductance Method.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021
A comparative study on the accuracy of small-signal equivalent circuit modeling for large gate periphery GaN HEMT with different source to drain length and gate width.
Microelectron. J., 2021

Robust and Secure Digital Image Watermarking Technique Using Arnold Transform and Memristive Chaotic Oscillators.
IEEE Access, 2021

2018
Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017
Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate Geometry.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2014
Temperature dependent subthreshold model of long channel GAA MOSFET including localized charges to study variations in its temperature sensitivity.
Microelectron. Reliab., 2014

2013
Numerical analysis of localised charges impact on static and dynamic performance of nanoscale cylindrical surrounding gate MOSFET based CMOS inverter.
Microelectron. Reliab., 2013

Drain current model for a gate all around (GAA) p-n-p-n tunnel FET.
Microelectron. J., 2013

2012
Immunity against temperature variability and bias point invariability in double gate tunnel field effect transistor.
Microelectron. Reliab., 2012

Simulation study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for high temperature applications.
Microelectron. Reliab., 2012

Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range.
Microelectron. Reliab., 2012

Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis.
Microelectron. Reliab., 2012


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